Monitoring PLL lock status on ADRV9026

ADRV9026 has 5 different PLLs that can be used based on the profile configuration being used. The user can monitor the lock status for each of the PLLs being used in two different ways using API and via GP int pins. The user can call the API function adi_adrv9025_PllStatusGet to retrieve the current lock status of each of the PLLs (except SERDES PLL). The user can also use the API function adi_adrv9025_GpIntStatusGet  to retrieve the PLL status and check if any of the PLLs had any loss of lock. The user can use the GP int pins to get real time access of the PLL lock status. The GP INT pins can be muxed to the PLL unlock sources to monitor the loss of lock events for each of the PLLs. The user can refer to GENERAL PURPOSE INTERRUPT section in the ADRV9026 user guide for detailed information. Please note that the user should unmask the CP Overrange Event Bits for the GPINT pins. These bits may assert intermittently but do not indicate a significant device issue.

The PLL unlock event bits, if asserted, indicate that a PLL has unlocked and is not operating properly. The PLLs are designed to maintain lock over the full temperature range and operation of the device. In extremely rare cases the PLL may unlock due to external or internal factors. There are two recovery procedures for PLL unlocks depending on the PLL that unlocks.

• If CLK PLL or SERDES PLL unlocks:
  • Reset Device. It is not expected the device can recover from the loss of the primary clock within the transceiver.
• If LO2, LO1 or Aux PLL unlocks
  • If the unlocked PLL re-locks, then follow procedures to re-run certain initialization calibrations as this is effectively a PLL frequency change procedure. If the user has configured attenuation ramp down/up events to occur based on PLL lock status, the attenuation ramp down/up event must be cleared prior to running initial calibrations.
  • If the unlocked PLL fails to achieve lock, then reset the device.
  • Call adi_adrv9025_PllFrequencySet(…) to see if the PLL re-locks.

The user can test out their GP INT set up and check if it responds to different PLL unlock events using the following experiments –

1. RF1 PLL unlock event – After setting up the GP INT mask as mentioned in the user guide, the user would need to write the register 0x2A02 to 0xF to completely power down the RF1 PLL. This would cause the GP INT status to be asserted and assert the corresponding GP INT pin. The user can check that the RF1 PLL is unlocked using the API function adi_adrv9025_PllStatusGet.

2. RF2 PLL unlock event – After setting up the GP INT mask as mentioned in the user guide, the user would need to write the register 0x6402 to 0xF to completely power down the RF2 PLL. This would cause the GP INT status to be asserted and assert the corresponding GP INT pin. The user can check that the RF2 PLL is unlocked using the API function adi_adrv9025_PllStatusGet.

3. AUX PLL unlock event – After setting up the GP INT mask as mentioned in the user guide, the user would need to write the register 0x2602 to 0xF to completely power down the AUX PLL. This would cause the GP INT status to be asserted and assert the corresponding GP INT pin. The user can check that the AUX PLL is unlocked using the API function adi_adrv9025_PllStatusGet.

4. SERDES PLL unlock event – After setting up the GP INT mask as mentioned in the user guide, the user can clear bit 0 of the register 0x6846. This will cause SERDES PLL to unlock and assert the corresponding GP INT pin.

5. CLK PLL unlock event – After setting up the GP INT mask as mentioned in the user guide, the user would need to write the register 0x2802 to 0xF to completely power down the CLK PLL. This would cause the GP INT status to be asserted and assert the corresponding GP INT pin. The user can check that the CLK PLL is unlocked using the API function adi_adrv9025_PllStatusGet.

The user would need to reset the device after running each of the above tests. Please note that these experiments should only be used during lab evaluation.