KCC's Quizzes AQQ304 - A pure logic
1. Quote of the month: "I am not lazy, I'm just in energy-saving mode" - unknown
2. Quiz AQQ304 about finding a pure logic puzzle
Mike is looking at Anne, but Anne is looking at Paul.
Mike is married, but Paul is not.
Question:
Is a married
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August Monthly Blog Quiz! Read the blog, take the quiz, and you could win a gift card
Important: Read the blog first . The quiz questions are all based on the content of the blog:
Stay in the loop and win! Read the blog Current Output Driving Industrial Loops , then take our quick five-question quiz for a chance to win a gift card
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ADRV9009
Recommended for New Designs
The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital...
Datasheet
ADRV9009 on Analog.com
I am using single talise chip in my design. DO I need to call TALISE_enableMultichipSync() API function and what its return value means?
__CommunityServer__Service__ - Moved from TES GUI & Software support ADRV9009/ADRV9008-1/ADRV9008-2 to Design Support ADRV9008-1/ADRV9008-2/ADRV9009. Post date updated from Friday, June 8, 2018 10:56 AM UTC to Thursday, January 22, 2026 7:09 PM UTC to reflect the move.
multichip sync is required to configure JESD deterministic latency. Please refer API documentation to understand in more details.
so just to be 100% clear on this : the multi-chip sync function is not only meant to be used with 'multiple-ADRV9009'? It should also be used to 1x ADRV9009 connected to an FPGA through JESD?, to get the latency between 1 ADRV9009 and the FPGA fixed between different 'power-cycles' or JESD (re)connects?
Yes. Please refer User guide for more details.
For RF PLL phase sync , there is another feature called RF PLL phase synchronization. (please refer UG-1295)