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ADRV9009 MCS

Thread Summary

The user asks if the TALISE_enableMultichipSync() API function is necessary for a single TALISE chip design. The final answer confirms that multichip sync is required to configure JESD deterministic latency, and the accompanying answers clarify that this function should also be used for a single ADRV9009 connected to an FPGA to fix latency between power cycles or JESD reconnects. The RF PLL phase synchronization feature is also mentioned for additional phase sync requirements.
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I am using single talise chip in my design. DO I need to call TALISE_enableMultichipSync() API function and what its return value means?

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