Custom board. Synchronization of data between two ADRV9009 chips.

Chernihiv said:

Is it possible to align the lines for only each ADRV9009 individually, or do all lines have to be length-aligned?

You need to align the lanes per ADRV9009 (per JESD link).

Chernihiv said:

. What are the restrictions on the JESD lines for multi-chip synchronization? (

There are no restrictions as such.

• The SYSREF and DEVCLK should be source synchronous. 
• Meet the setup and hold times for SYSREF signals relative to the device clock. 
• For proper synchronization, the rising edge of SYSREF must be received at each device during the same device clock cycle.
• For MCS , we need three sysref pulses from clock device. Refer to "MULTICHIP SYNCHRONIZATION" section from UG page 54 for details. 

Chernihiv said:

Is it possible to align the lines for only each ADRV9009 individually, or do all lines have to be length-aligned?

You need to align the lanes per ADRV9009 (per JESD link).

Chernihiv said:

. What are the restrictions on the JESD lines for multi-chip synchronization? (

There are no restrictions as such.

• The SYSREF and DEVCLK should be source synchronous. 
• Meet the setup and hold times for SYSREF signals relative to the device clock. 
• For proper synchronization, the rising edge of SYSREF must be received at each device during the same device clock cycle.
• For MCS , we need three sysref pulses from clock device. Refer to "MULTICHIP SYNCHRONIZATION" section from UG page 54 for details. 

Thank you very much)

vanitha said:

vice clock cycle.