FIFO on the Rx path of ADRV9009?

So we have to do multiple power reboots, multiple tests, to gain some confidence that our value is good? But may be not optimal... On what depends this value? With another board (sample) of the same model, should the result be the same?

tcachat said:

So we have to do multiple power reboots, multiple tests, to gain some confidence that our value is good?

Yes, after multiple reboots the latency should be constant .

tcachat said:

With another board (sample) of the same model, should the result be the same?

It's better to verify on 5 or more samples and fix the LMFC offset value.

tcachat said:

So we have to do multiple power reboots, multiple tests, to gain some confidence that our value is good?

Yes, after multiple reboots the latency should be constant .

tcachat said:

With another board (sample) of the same model, should the result be the same?

It's better to verify on 5 or more samples and fix the LMFC offset value.