ADRV9009
Recommended for New Designs
The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital...
Datasheet
ADRV9009 on Analog.com
Is there a FIFO on the Rx path of ADRV9009? Similar to that of the Tx path?
From UG-1295: "The FIFO depth can be checked in Register 0x15CE for Deframer 0 and in
Register 0x161E for Deframer 1." Is there something similar for the Framers A and B?
I have observed that the Rx latency can increase by 32 samples from reboot to reboot (randomly). Then I have changed .framerA.lmfcOffset from 31 to 15, and it seems it has solved the issue.
Typically adjust LMFC offset ,check latency consistency and then check whether the Link is stable /latency is deterministic or if we have any JESD link errors.
Even after multiple power reboots , the latency should be constant. In that case the lmfc offset which you set would be good.
Typically adjust LMFC offset ,check latency consistency and then check whether the Link is stable /latency is deterministic or if we have any JESD link errors.
Even after multiple power reboots , the latency should be constant. In that case the lmfc offset which you set would be good.