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FIFO on the Rx path of ADRV9009?

Category: Datasheet/Specs
Product Number: ADRV9009

Is there a FIFO on the Rx path of ADRV9009? Similar to that of the Tx path?

From UG-1295: "The FIFO depth can be checked in Register 0x15CE for Deframer 0 and in
Register 0x161E for Deframer 1." Is there something similar for the Framers A and B?

I have observed that the Rx latency can increase by 32 samples from reboot to reboot (randomly). Then I have changed .framerA.lmfcOffset from 31 to 15, and it seems it has solved the issue.

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  • Dear , you can read in my first post "it seems it has solved the issue". But I would prefer to be sure.

    Is there a way to know that my setting for .framerA.lmfcOffset is good? (like the known way for Deframer)

    The setup is the following: we have a custom board with an ADRV9009, we set one channel in Tx, the other in Rx, we connect both channels together with a cable outside of the board, and we measure the time between transmission and reception (of the first non zero I/Q data, for example).

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  • Dear , you can read in my first post "it seems it has solved the issue". But I would prefer to be sure.

    Is there a way to know that my setting for .framerA.lmfcOffset is good? (like the known way for Deframer)

    The setup is the following: we have a custom board with an ADRV9009, we set one channel in Tx, the other in Rx, we connect both channels together with a cable outside of the board, and we measure the time between transmission and reception (of the first non zero I/Q data, for example).

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