FIFO on the Rx path of ADRV9009?

tcachat said:

Is there a FIFO on the Rx path of ADRV9009? Similar to that of the Tx path?

No.

tcachat said:

have observed that the Rx latency can increase by 32 samples from reboot to reboot (randomly). Then I have changed .framerA.lmfcOffset from 31 to 15, and it seems it has solved the issue.

Is the issue solved? 

If not, can you please provide test setup details?

Dear vanitha , you can read in my first post "it seems it has solved the issue". But I would prefer to be sure.

Is there a way to know that my setting for .framerA.lmfcOffset is good? (like the known way for Deframer)

The setup is the following: we have a custom board with an ADRV9009, we set one channel in Tx, the other in Rx, we connect both channels together with a cable outside of the board, and we measure the time between transmission and reception (of the first non zero I/Q data, for example).

Typically adjust LMFC offset ,check latency consistency and then check whether the Link is stable /latency is deterministic or if we have any JESD link errors.

Even after multiple power reboots , the latency should be constant. In that case the lmfc offset which you set would be good.

So we have to do multiple power reboots, multiple tests, to gain some confidence that our value is good? But may be not optimal... On what depends this value? With another board (sample) of the same model, should the result be the same?

tcachat said:

So we have to do multiple power reboots, multiple tests, to gain some confidence that our value is good?

Yes, after multiple reboots the latency should be constant .

tcachat said:

With another board (sample) of the same model, should the result be the same?

It's better to verify on 5 or more samples and fix the LMFC offset value.