Hello,
A customer intends to reduce the number of Tx JESD lanes from 8 to 4 and drop the sampling frequency from 491.52MHz to 245.76MHz and maintain a lane rate of 9.83Gbps.
What changes are needed to the HDL and SW?
We suggested updating the device tree, and the customer made these changes:
&trx0_adrv9009
{ adi,tx-profile-dac-div = <2>; adi,jesd204-deframer-a-deserializer-lanes-enabled = <0x3>; adi,jesd204-deframer-a-deserializer-lane-crossbar = <0x4>; adi,tx-profile-tx-input-rate_khz = <122880>; }
;
&trx1_adrv9009
{ adi,tx-profile-dac-div = <2>; adi,jesd204-deframer-a-deserializer-lanes-enabled = <0x3>; adi,jesd204-deframer-a-deserializer-lane-crossbar = <0x4>; adi,tx-profile-tx-input-rate_khz = <122880>; }
;
&axi_adrv9009_tx_jesd
{ adi,octets-per-frame = <4>; }
;
But they receive this error:
[ 417.906182] axi_adxcvr_drv 84a60000.axi-adxcvr-rx-os: adxcvr_clk_enable: CPLL RX buffer underflow error, status: 0x61
[ 417.916804] axi_adxcvr_drv 84a60000.axi-adxcvr-rx-os: adxcvr_clk_enable: CPLL RX buffer overflow error, status: 0x61
Any insight into what they need to do differently?