I got an error when using the adrv9009 no_os program:
tx_adxcvr: adxcvr_drp_wait_idle: Timeout!ERR: ../src/platform/xilinx_transceiver.c:141:xilinx_xcvr_drp_read(): xilinx_xcvr_drp_read: Failed to read reg 16-0x0014: -1
hardware information:
FPGA is XCZU19EG-ffvc1760-2, clock is 2 pcs of hmc7044, transceiver is 8 pcs of adrv9009, each HMC7044 provides clocks for four ADRV9009 chips.
Develop using Vivado 2022.2 and Vitis 2022.2
Refer to the XCZU102 + FMCOMMS8 project and configure IP cores such as xcvr and jesd to 32 lanes.
It is normal to conduct tests with the first HMC7044 and the first four ADRV9009s, and it is also normal to conduct tests with the second HMC7044 and the last four ADRV9009s. The projects for these two tests also refer to the XCZU102 + FMCOMMS8 project, and the IP cores such as XCVR and JESD are configured to 16 lanes.
So I think there should be no problem with my hardware. However, the project of 8 ADRV9009 chips will report an error at fpga_xcvr_init(). May I ask how I should troubleshoot it?