Hello,
We are facing an issue related to the serializer lane crossbar configuration in the ADRV9009.
System Description:
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We are using a custom ADRV9009 board.
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The SERDIN pins from the ADRV9009 are routed to the FPGA without any lane swap on the PCB.
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Framer A is used for RX data.
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Framer B is used for ORx data.
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We are using the SDK and RTL provided from the ADI GitHub repository as reference.
Configuration Details:
Since there is no physical lane swap, we attempted to enable manual lane crossbar configuration in talise_config.c with the following settings:
Framer A (RX)
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Lanes enabled: 0x03
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Serializer lane crossbar: 0xF4
Framer B (ORx)
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Lanes enabled: 0xC0
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Serializer lane crossbar: 0x4F
With this configuration, JESD initialization gets stuck in the CGS state.
However,
When we disable manual lane crossbar configuration (keeping the same lane enable settings), initialization completes successfully.
Upon checking talise_jesd204.c, we observed that when manual crossbar is disabled, the driver automatically assigns:
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Framer A crossbar value: 0xDC
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Framer B crossbar value: 0x73
These values are internally derived based on the enabled lanes.
Our Confusion:
We are unclear about:
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How the lane mapping and crossbar values are derived internally when manual configuration is disabled.
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Why manual crossbar values (0xF4 / 0x4F) cause CGS failure while auto-assigned values (0xDC / 0x73) work correctly.
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What the correct mapping methodology should be when there is no PCB-level lane swap.
Could you please help clarify:
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The correct relationship between lanes enabled mask and serializer lane crossbar value?
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How to properly calculate/program the crossbar when manual configuration is required?
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Why this CGS failure is being observed in our case?
Thank you for your support.
