I build the no-os project with iio_enable and it can be connected
the first couple frames look normal
after few frame the adc data capture looks weired
I understand the uart speed is too low for transmit adc data. is this normal or there is something wrong with my hdl design. the dma_example output looks normal
Xilinx Zynq MP First Stage Boot Loader
Release 2022.2 Feb 15 2026 - 02:46:57
PMU-FW is not running, certain applications may not be supported.
Hello
rx_clkgen: MMCM-PLL locked (122880000 Hz)
tx_clkgen: MMCM-PLL locked (61440000 Hz)
rx_os_clkgen: MMCM-PLL locked (61440000 Hz)
rx_adxcvr: OK (4915200 kHz)
tx_adxcvr: OK (2457600 kHz)
rx_os_adxcvr: OK (2457600 kHz)
talise: Device Revision 192, Firmware 6.2.1, API 3.6.2.4294967297
talise: Calibrations completed successfully
rx_jesd status:
Link is enabled
Measured Link Clock: 122.893 MHz
Reported Link Clock: 122.880 MHz
Lane rate: 4915.200 MHz
Lane rate / 40: 122.880 MHz
LMFC rate: 3.840 MHz
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No
tx_jesd status:
Link is enabled
Measured Link Clock: 61.446 MHz
Reported Link Clock: 61.440 MHz
Lane rate: 2457.600 MHz
Lane rate / 40: 61.440 MHz
LMFC rate: 3.840 MHz
SYNC~: deasserted
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No
rx_os_jesd status:
Link is disabled
Measured Link Clock: 61.446 MHz
Reported Link Clock: 61.440 MHz
External reset is deasserted
tx_dac: Successfully initialized (122891235 Hz)
rx_adc: Successfully initialized (122891235 Hz)
rx_os_adc: Successfully initialized (122891235 Hz)
Rx DMA_EXAMPLE: address=0x800000 samples=65536 channels=4 bits=16
Running IIOD server...
If successful, you may connect an IIO client application by:
1. Disconnecting the serial terminal you use to view this message.
2. Connecting the IIO client application using the serial backend configured as shown:
Baudrate: 921600
Data size: 8 bits
Parity: none
Stop bits: 1
Flow control: none
and How can I change TX/RX carriage frequency in no-os app? can't find this config..
best regards
