Effect of REF_CLK_IN frequency on RF PLL phase settling time when frequency hopping

gavint said:

o would we see any reduction in the RF PLL phase synchronisation settling time by using a 983.04MHz (245.76MHz x 4) REF_CLK_IN frequency instead?

Yes this might help in reducing the RF PLL phase synchronization settling time .

Can you please share us the setup diagram of how you are testing ?

Are you able to achieve the phase synchronization with 2 ADRV9009 devices ?

 RE: ADRV9008_1 multichip phase  sync lost after frequency hopping 

Hello Vanitha

Thank you for responding to my questions.

To confirm, I am using the JESD204B FSM. If we slow down the frequency hopping, we can see that the relative phase does stabilise. Also, if we do not perform frequency hopping then the phases are stable and repeatable across power cycles. I think this shows that the JESD204B FSM and multi-chip phase synchronisation is working as expected.

Here is a block diagram of our test setup:

The first ADRV9009 device generates an output tone to a splitter. This is the calibration tone. The splitter then sends this tone to all the RX inputs of the three ADRV9009 devices. The FPGA captures multiple blocks of data from each RX. An FFT is performed. At a specific bin in the FFT (corresponding to the location of the calibration tone), the phases of the channels are compared relative to ADRV9009 1 RX1 across the multiple block captures.

This is plotted below:

The green plot is ADRV9009 1 RX2 compared to ADRV9009 1 RX1. As you can see, within an ADRV9009 device, relative changes in the LO phase are not picked up because the same LO is used for both RX1 and RX2. The other plots show how the phases of the other ADRV9009 devices settle relative to ADRV9009 1. The total period across all these block captures is 25 ms. In this specific test case you can see that the LO multisync phase stabilises within roughly 10 ms. The total phase variation is 4 degrees at 5.8GHz LO frequency.

I will test if increasing the REF_CLK_IN frequency will reduce the time taken for the multisync phase alignment to stabilise.

Thank you.

Gavin

Try with increasing the REF CLK frequency and see if it reduces the RF PLL phase synchronization settling time.

I can now confirm that increasing the REF_CLK_IN frequency has no major impact on the time taken for the phases to stabilise across the three ADRV9009 devices.

I wasn't able to test with 983.04MHz (245.76MHz x 4) REF_CLK_IN because the ADRV9009 devices would fail a calibration step during the Linux boot up. But I was able to test with 491.52MHz (245.76MHz x 2) REF_CLK_IN. 

Although this is only two times higher frequency, it should have at least cut the phase settling time in half if the ADRV9009 multi-chip phase synchronisation depended solely on the REF_CLK_IN frequency. But since it made no noticeable impact, I can only think that the ADRV9009 ARM software takes the frequency of REF_CLK_IN into account.

Would you expect any difference by setting the RF PLL loop bandwidth to the maximum (750kHz)? What would be the drawback of making this change?

Any other ideas or suggestions would be greatly appreciated.

Thank you.