I/Q data mixed up in JESD?

This could be related to signal integrity issue .

Can you try reading back the framer/deframer status when issue is seen?

Also can you try testing PRBS test and see if it passes?

Thank you vanitha

I read

DeframerStatus=0x86 

FramerStatus=0x25

independently of the issue: I get the same status with and without the issue. These status seems correct?

Sometimes I read DeframerStatus=0x8E (adding bit "LMFC out", "Not useful to read across SPI"), but also independently of the issue. By repeated reading, 0x8E appears randomly.

I have found some functions to check PRBS on the ADRV9009 deframer side, but it is unclear to me how I can configure the FPGA to send a PRBS.

Hello tcachat, 

Please provide the output of the jesd_status command.

Regarding your last question, write to the address:  tx_adrv9009_tpl_core + 0x418 + 0x40 * n, where n is the channel number, using one of the following values depending on the desired data source: 

• 0x00: internal tone (DDS)
• 0x01: pattern (SED)
• 0x02: input data (DMA)
• 0x03: 0x00
• 0x04: inverted pn7
• 0x05: inverted pn15
• 0x06: pn7 (standard O.150)
• 0x07: pn15 (standard O.150)
• 0x08: loopback data (ADC)
• 0x09: pnX (Device specific e.g. ad9361)
• 0x0A: Nibble ramp (Device specific e.g. adrv9001)
• 0x0B: 16 bit ramp (Device specific e.g. adrv9001)

Kind regards,

Bianca

Thank you CapotaBianca 

From a point where the RF output is what I expect (green wave on scope above), using the addresses you give and pn7 or pn15 on the appropriate lane produces a noisy RF output, as expected.

Nevertheless, PRBS error counter in ADRV9009 are always 255, using TALISE_enableDeframerPrbsChecker, TALISE_clearDeframerPrbsCounters, TALISE_readDeframerPrbsCounters as suggested by vanitha . I have checked with TAL_PRBS7 and TAL_PRBS15. I presume I cannot use TAL_PRBS31.

What do you mean by jesd_status command? As above, I read 

DeframerStatus=0x86

FramerStatus=0x25

And sometimes I read DeframerStatus=0x8E (see above)

Regards

Hello tcachat , 

Information about jesd_status can be found here:JESD204B Status Utility

Best regards,

Bianca

Dear CapotaBianca ,

We have a custom board without Linux ("no-OS driver"). I can use functions from the API (as above), and access to the FPGA (as above). In that sense I have used following code (extract):

TALISE_enableDeframerPrbsChecker( &talDev, TAL_PRBS15, TAL_PRBSCHECK_LANEDATA);
TALISE_clearDeframerPrbsCounters( &talDev);
TALISE_readDeframerPrbsCounters( &talDev, iLane, &prbsErrorCount, &prbsInvertedStatus);

TALISE_readDeframerStatus(&talDev, TAL_DEFRAMER_A, &deframerStatus);
TALISE_readFramerStatus(&talDev, TAL_FRAMER_A, &framerStatus);

Regards

Hi tcachat, 

We’re sorry to inform you that the colleagues responsible for this project are currently unavailable due to the holiday season. We will gladly provide the necessary support once they return in January.

Thank you for your understanding!

Best regards,

Bianca

Hi CapotaBianca and vanitha 

I was also on holidays. I hope you are also back!

Happy new year!

Dear CapotaBianca  and vanitha 

Can you please tell m:

- how to check JESD20B Status from the API? (without Linux, see above)

- how to test PRBS signal on JESD? (seems I can configure the FPGA to send a PRBS, but how to check on the ADRV side? see above)

- should I move the post to "Design Support ADRV9008-1/ADRV9008-2/ADRV9009"? (suggested by the site)

Regards

Hello tcachat, 

You can obtain JESD link information directly from the JESD204 registers.

For RX, please refer to the register map here: JESD204 RX register map.

Also, for TX, the register map is available here: JESD204 TX register map.

These registers allow you to read the JESD link status.

Moving this thread to the (Missing Group) forum for further support.

Best regards,

Bianca

Hello CapotaBianca 

attached are the values of the JESD Tx registers I can read in the FPGA. Can you have a look at them? Unfortunately I get the same values with and without the issue.

7701.JESDresgisters.txt

Hello CapotaBianca and vanitha ,

Our issue might be related to another one: the latency of the JESD+ADRV9009 is slightly variable and (for now) unpredictable. Could it be a (strange) latency problem, where every second chunk of 16 I/Q data points have a different latency (somewhere between our user code in the FPGA and the RF output).

Hello CapotaBianca and vanitha ,

Our issue might be related to another one: the latency of the JESD+ADRV9009 is slightly variable and (for now) unpredictable. Could it be a (strange) latency problem, where every second chunk of 16 I/Q data points have a different latency (somewhere between our user code in the FPGA and the RF output).