Category: Datasheet/Specs
Hi,
I'm integrating the ADRV9008-1 with a Xilinx KU115 FPGA via custom RTL for SPI/ JESD communication, without using a soft processor like MicroBlaze due to high resource consumption concerns. The datasheets and UG-1295 manual don't include a direct register map
I've checked the no-OS API source on GitHub (talise_reg_addr_macros.h), which seems to contain register address macros used for talSpiWrite/talSpiRead. However, for bare-metal RTL implementation:
- Is there a complete, official SPI/JESD register map (addresses, bit fields, read/write sequences) available?
- Are there any guidelines or examples for direct register access without the full API?
- Or can you suggest any other methods to implement the same.
