Necessity to use external reference clock to PLL1 of AD9528

are you using the ADRV9008-2 eval board or the custom board? In the first case that you mentioned with 245.76 MHz, how are you feeding the clock input to the AD9528 chip? 

Hi  RR4 

We are using ADRV9008-2 Evaluation board which also has AD9528 chip along with on-board crystek VCXO that gives input of 122.88MHz input to AD9528. When no REFA is provided to AD9528 chip, the output of DAC in terms of constellation seems unstable (rotations are observed for higher modulation scheme), however, when an external reference REFA of 30.72MHz from a signal generator is provided (along with VCXO), the constellation seems stable. 

Requesting to provide inputs to avoid using the external reference in order to obtain a clean constellation.

Thanks

Deepika

To ensure that the PLL1 of AD9528 is locked, you should use the external clock. Currently, the internal 122.88 MHz VCXO PLL1 output is not locked, causing instability in the constellation and resulting in rotation. This instability is due to frequency drift. By using an external clock, you can obtain better results for the EVM and synchronize the clock and equipment to achieve improved performance.

Hi RR4 

Thanks for the response.

Yes, in our current setup, by using an external clock, we are able to obtain better results for EVM, however our application is to get better EVM results without this external clock, i.e., we are trying to use AD9528 in Single Loop mode (in which PLL1, REFA and REFB inputs to AD9528 are off), and to operate AD9528 in this mode, the following changes were done in app_clocking.c file of AD, where the following parameters were changed : 

ad9528_param.pdata->refa_en = 0;// earlier it was set to 1;

ad9528_param.pdata->refa_diff_rcv_en = 0;//  --earlier set to 1
ad9528_param.pdata->refa_r_div = 0;//1; --earlier set to 1

ad9528_param.pdata->pll1_bypass_en = 1;//0;      --earlier set to 0

However, on making these changes, the constellation was found stable for a short time and rotations were still observed. The code snippet is with necessary changes for single loop mode is attached for reference.

// ad9528 settings
	ad9528_param.pdata->spi3wire = 0;
	ad9528_param.pdata->vcxo_freq = 122880000;
	ad9528_param.pdata->refa_en = 0;//1;       --earlier set to 1
	ad9528_param.pdata->refa_diff_rcv_en = 0;//1;       --earlier set to 1
	ad9528_param.pdata->refa_r_div = 0;//1;    --earlier set to 1
	ad9528_param.pdata->osc_in_cmos_neg_inp_en = 1;
	ad9528_param.pdata->pll1_feedback_div = 4;
	ad9528_param.pdata->pll1_feedback_src_vcxo = 0; /* VCO */
	ad9528_param.pdata->pll1_charge_pump_current_nA = 5000;
	ad9528_param.pdata->pll1_bypass_en = 1;//0;      --earlier set to 0
	ad9528_param.pdata->pll2_vco_div_m1 = 3;
	ad9528_param.pdata->pll2_n2_div = 10;
	ad9528_param.pdata->pll2_r1_div = 1;
	ad9528_param.pdata->pll2_charge_pump_current_nA = 805000;
	ad9528_param.pdata->pll2_bypass_en = false;
	ad9528_param.pdata->sysref_src = SYSREF_SRC_INTERNAL;
	ad9528_param.pdata->sysref_pattern_mode = SYSREF_PATTERN_CONTINUOUS;
	ad9528_param.pdata->sysref_req_en = true;
	ad9528_param.pdata->sysref_nshot_mode = SYSREF_NSHOT_4_PULSES;
	ad9528_param.pdata->sysref_req_trigger_mode = SYSREF_LEVEL_HIGH;
	ad9528_param.pdata->rpole2 = RPOLE2_900_OHM;
	ad9528_param.pdata->rzero = RZERO_1850_OHM;
	ad9528_param.pdata->cpole1 = CPOLE1_16_PF;
	ad9528_param.pdata->stat0_pin_func_sel = 0x1; /* PLL1 & PLL2 Locked */
	ad9528_param.pdata->stat1_pin_func_sel = 0x7; /* REFA Correct */
#endif

How to obtain a stable clock output from AD9528 in Single loop mode without using external clock.

-Deepika

Are you using the ADRV9008-2 board for this testing? How do you intend to supply the clock signal to the custom board? Is it through GPS clock synchronization or the TCXO/OCXO main clock in the system? If you are using the ADRV9008-2 board, an external clock will be necessary to achieve the proper EVM (error vector magnitude) and ensure that the external clock source and equipment are synchronized for accurate results. If you plan to use the board without an external clock, you will need a clock recovery algorithm to compensate for frequency drift.

For any queries related to AD9528, please open a new thread with your questions. Here is the link for the AD9528 forum.

https://ez.analog.com/clock_and_timing/f/q-a

Are you using the ADRV9008-2 board for this testing? How do you intend to supply the clock signal to the custom board? Is it through GPS clock synchronization or the TCXO/OCXO main clock in the system? If you are using the ADRV9008-2 board, an external clock will be necessary to achieve the proper EVM (error vector magnitude) and ensure that the external clock source and equipment are synchronized for accurate results. If you plan to use the board without an external clock, you will need a clock recovery algorithm to compensate for frequency drift.

For any queries related to AD9528, please open a new thread with your questions. Here is the link for the AD9528 forum.

https://ez.analog.com/clock_and_timing/f/q-a

Hi RR4 

Yes, we are using ADRV-9008-2 evaluation board that is configured using ZCU102 evaluation board. 

Well, in case of custom card, it is in design stage and our confidence was to use AD9528 in single loop mode to avoid the requirement of external clock, but we may have to rethink on this, considering the performance of AD9528 .

Also, initially this query was posted in AD9528 forum :  Necessity to use External reference clock for PLL1 of AD9528 , however, I was asked to create a new thread in ADRV9008-2 forum.

Thanks for your suggestions.

-Deepika

Hi Deepika, I suggest you post a question specific to the AD9528 part to single loop mode to get more details.

If you need any details to ADRV9008-2 please let me know.