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Multiple adrv9009 multiple chip sync

Category: Hardware

Hi, ADI

Now, I have master-slave 7044 clock tree architecture, the master 7044 generate clock signal for 4 slaver 7044. A clock provided from a slaver 7044 to 2 pieces of adrv9009. Now, we have achieved clock synchronization from 4 slaver 7044 output SYSREF and REFCLK. We use a signal source to input 8 signals simultaneously, and the relative phase between the received waveforms observed from VIVADO ILA will deviate after two power cycles, deterministic delay not implemented. The SYSREF signal is pulse request mode, every request from 7044 will simultaneously generate SYSREF pulses for adrv9009.  Which step went wrong? we setup step is ①setup 7044; ②initial JESD core; ③perform setup 8 adrv9009; ④perform 8 adrv9009 MCS

  • can you please provide the setup details to understand about the issue more? are you using the ADRV9009 eval board or custom board? 

  • We are using custom boards, and adrv9009 initial setup and MCS refer to UG1295

  • HI, In the MCS process of 9009, should I wait until the last chip of 9009 for MCS to request SYSREF to synchronize all 9009?

  • Can you share the block diagram of the testing setup ?

    Is the REF-CLK provided continuously to both the ADRV9009  boards?

    Make sure that the rising edge of SYSREF is received at each device during the same device clock cycle. Hope you are disabling SYSREF and then enabling MCS. 

    From UG:

    When multichip sync is enabled, the function is performed in four stages; each one is initiated with a rising SYSREF edge. The first two SYSREF rising edges synchronize the device clock dividers. This portion of the synchronization requires some amount of time for the clock PLL outputs to settle. The third SYSREF rising edge synchronizes the high speed digital clock dividers. The fourth SYSREF rising edge synchronizes the numerically controlled oscillators (NCOs), the JESD204B LMFC, and the RF PLL phase synchronization

    Can you readback the status of the MCS using enableMultichipSync() API ?

    Please check UG-1295 (page 54) on multi chip synchronization for more details.