ADRV9009 and AD9361: LO shows harmonics

Hello,

1. Indeed I was not clear about the number and spacing of harmonics. What I wanted to point out is that I see f_LO + 2*n*f_LO, n = 1, 2, 3,... and they are clearly visible in the figures I posted. 
2. I already tried that and mentioned in the original post that it did not change difference in powers between the harmonics. Only the total power went down, and the harmonics scaled down proportionally. That is the case for both our device and the USRP B210 with a different AD chip (an example attached). 

Best,
H.

Hello,

1. Indeed I was not clear about the number and spacing of harmonics. What I wanted to point out is that I see f_LO + 2*n*f_LO, n = 1, 2, 3,... and they are clearly visible in the figures I posted. 
2. I already tried that and mentioned in the original post that it did not change difference in powers between the harmonics. Only the total power went down, and the harmonics scaled down proportionally. That is the case for both our device and the USRP B210 with a different AD chip (an example attached). 

Best,
H.

can you please share the configuration that was used for the above testing, I will re-sue the same to test my side. harmonics performance will improve if we scale down the power.

I am afraid there is not much to share. For both devices the signal from a TX port goes into the spectrum analyzer over a short SMA cable with low loss. The spectrum analyzer was calibrated two months ago and can handle up to 1W. I never exceeded -10 dBm transmit power and as I illustrated, the problem remains no matter how much I lower the power until the harmonics disappear below the noise level.

1. Our device feeds the signal directly from ADRV9009 to the connector on the front panel. The FMCs are connected to the carrier board with ZYNQ UltraScale+ ZU7. These go into a MicroTCA chassis that provides power supply, Ethernet connection, etc. I used the "Single Tone" from the AD oscilloscope, and also FMCW from a custom Python script based on PyADI library.
2. USRP B210 was not modified in any way. I believe it uses AD9361, but in any case it is not ADRV9009. I used their uhd_siggen_gui utility as the signal generator.

I hope this helps,
H.

Thanks for sharing the details, I was asking about the ADRV9009 device configuration like LO frequency, bandwidth, sampling rate, and all. Can you please share the details I will use the same configuration for our testing.

Hello,

As I mentioned, I tried different carrier frequencies, including 500 MHz and 2 GHz. Regarding the rates, I tried full speed 245.76 Ms/s as well as 30.72 Ms/s (the FPGA image includes decimation/interpolation). I tried different Tx attenuation settings, for instance 10 dB and 30 dB. I also varied the signal amplitude from close to 0 to close to 1 normalized (or 2^15 - 1 in terms of full scale). For the case of lower sampling rate, the interpolation and decimation filters include means to prevent bit growth and consequently saturation and clipping.

In any case, it seems that the problem is not in the baseband. I did some additional search. Is it possible that the LO uses square or close to the square wave? 

Infineon datasheet (page 2)
MIT lecture (pages 21 - 26)

That would immediately explain the results (with some uncertainty and imperfections in measurements). When one looks into the Fourier series decomposition of a square wave it fits the pattern since only odd harmonics are present and they decay with 1/(2n+1) n = 0,1,2,...

If this is the issue, since ADRV9009 has so many settings, is there some way to attenuate these harmonics that I missed to enable? 

Cheers,
Haris

we don't have any knobs in the ADRV9009 to control the harmonics level, I will check the levels in my setup and update.