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Delay between the data coming out of ADRV9009 TX ports

Category: Software
Product Number: ADRV9009

I am sending same data (100MHz band) to all ADRV9009 channels from a data generator RTL module . I am able to see the spectrum out of all TX channels .

But the data out of different radios are having some delay like 4ns, 8ns .

Device clock for AD9528 is 245.76MHz (~4ns).

JESD link clock is also 245.76MHz. 

And , I observed that the delay between different radios is changing if the bitstream changes . Like , for one bitstream the delay might be 0 , for some other delay might be 4ns or 8ns.

Is there anything that I am missing . Can someone help me with this.

Thank you

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  • Hi  

    We are using custom FPGA board which is having 8 ADRV9009s and 2 AD9528s.

    Each AD9528 provides dev_clks to 4 of of the ADRV9009s.

    So four radios are getting ref clks from same AD9528 outputs.

    There is a delay between the four radios which are getting ref clk from same source.

  •  Considering the 4nsec delay difference is constant across reboots, below is my reply:

    Since, the delay difference is constant over boot to boot, that means phase sync is achieved between the boards. Now, if you want to align all the TX outputs , then you  can compensate for those delays either in your RTL or you can also add some delays in the DEV_CLK channel output of the AD9528’s. But you need to make sure by changing the DEV_CLK frequency that these delays  remains unchanged w.r.t the new DEV_CLK frequency. If its remains unchanged, then you can compensate for those fixed delays in your FPGA happening due to layout/trace length differences  . If the delays changes w.r.t DEV_CLK frequency, then you can adjust them by advancing or delaying the DEV_CLK channel output by half a clock cycle.