Delay between the data coming out of ADRV9009 TX ports

can you please confirm that are you using the ADRV9009 eval board or the custom board?

are you using the same reference clock between the radios?

Hi RR4 

We are using custom FPGA board which is having 8 ADRV9009s and 2 AD9528s.

Each AD9528 provides dev_clks to 4 of of the ADRV9009s.

So four radios are getting ref clks from same AD9528 outputs.

There is a delay between the four radios which are getting ref clk from same source.

 Considering the 4nsec delay difference is constant across reboots, below is my reply:

Since, the delay difference is constant over boot to boot, that means phase sync is achieved between the boards. Now, if you want to align all the TX outputs , then you  can compensate for those delays either in your RTL or you can also add some delays in the DEV_CLK channel output of the AD9528’s. But you need to make sure by changing the DEV_CLK frequency that these delays  remains unchanged w.r.t the new DEV_CLK frequency. If its remains unchanged, then you can compensate for those fixed delays in your FPGA happening due to layout/trace length differences  . If the delays changes w.r.t DEV_CLK frequency, then you can adjust them by advancing or delaying the DEV_CLK channel output by half a clock cycle.