Post Go back to editing

ADRV9009 Rx1 and Rx2 inconsistent behaviour for different power-cycles

Category: Software
Product Number: ADRV9009 viv
Software Version: Vivado 2021.2

Hi Team,

Referring to the previous forum post query: https://ez.analog.com/rf/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/163477/adrv9009-rx1-and-rx2-randomly-give-incorrect-data/374229, the problem is exactly as mentioned there, to quote it:"

The problem is, ADC data in ILA core is not correct. Whenever I program the FPGA, out of 4 of these cases, one of them occur randomly.

1. Data on both ADC is garbage,
2. ADC0 is garbage and ADC1 is showing a 1MHz tone(correct)
3. ADC1 is garbage and ADC0 is showing a 1MHz tone(correct)
4. Data on both ADC0 and ADC1 is correct.

"

The final solution that has been arrived upon is changing board. I have changed 3 boards & still the issue is recurrent across all setups. I don't see it to be a board issue, but something else. Request for guidance in debugging this issue.

 

Thanks & Regards

Goli Ganesh

  • ADI North America will be on summer shutdown starting August 24, 2023; perhaps another community member can assist you until our return on September 5th.
  • Can you please try doing a Tx-Rx loopback in your FPGA and see if you are getting data correctly at the FPGA ILA output or not ?

  • Hi  

            I tried the setup you mention, but I still have garbage data in the runs that are inconsistent. My application requires consistency from power-on to power-on. I have tried other things as well to address this issue, like changing boards as mentioned in the previously mentioned Forum Post. Request you to help me debug this issue and solve it.

    Thanks & Regards

    Goli Ganesh

  • It may be a JESD link issue . Can you please check the Framer status, in all these 4 cases ?

    And also can you please check the deframer status and do you see consistent power output from power up to power up?

     Have you tried testing the signal integrity of the lanes using PRBS generator and checker present in the chip

  • Hi  ,
     

                    Sorry for the delayed response.

    The link I posted initially shows "page not found".

    Here is the correct link to the same:  RE: ADRV9009 Rx1 and Rx2 Randomly Give Incorrect Data. 

    Can you please check the Framer status, in all these 4 cases ?

    And also can you please check the deframer status and do you see consistent power output from power up to power up?

          I checked the framer & de-framer status in multiple-power-cycles. I observed the values for them to be the same. In the 4-cases also, I observed the same results.

    Framer and de-framer status for CHIP-1 is:

    tal_framer_A: 0X21

    tal_framer_B: 0X29

    tal_deframer_A: 0X12

    tal_deframer_B: 0X110

    Framer and de-framer status for CHIP-2 is:

    tal_framer_A: 0X5

    tal_framer_B: 0XD

    tal_deframer_A: 0X86

    tal_deframer_B: 0X110

    I think that the tal_framer_A, tal_framer_B, Tal_deframer_A of CHIP-1 is not as per the ADRV9009 standard framer results. Only CHIP-2 values are matching to the standard results.

    Have you tried testing the signal integrity of the lanes using PRBS generator and checker present in the chip

    I checked the lanes of both TX & RX in CHIP-1 & CHIP-2, and I think it is ok. Side-note: I am using ZCU102_FMCOMS8 build.

     

    Awaiting your response on the above information.

    Thanks & Regards

    Goli Ganesh

  • The deframer status should be 0x86 and framer status should be 0x25.

    What is the status of SYNC signal ?

  • Hi ,

             Thank you for your response. Here are the observations: SYNC is always high. The link status is always in DATA state only, and there are no issues related to JESD initializations. The no-os initializations are ok, but there are 3 warnings related to chip-1 framer status & de-framer status:

    warning: TAL_DEFRAMER_A status 0x12

    warning: TAL_FRAMER_A status 0x21

    warning: TAL_FRAMER_B status 0x29

    It is working, but in some power-cycles, noise is coming in receiver data, though input is applied. Please refer the previously shared query:  RE: ADRV9009 Rx1 and Rx2 Randomly Give Incorrect Data. 

    Please let me know on how to debug this further. 

    Thanks & Regards

    Goli Ganesh

  • From the above log shared seems deframer and framer status is 0x12 and 0x21 which is incorrect ,should be 0x86 and 0x25 respectively . 

    From the deframer status it indicates FS Lost error (framing error).

    This can be caused by :

    -> Excessive intra lane skew. For this can you try using single lane and see if you don't see issue .

    -> Polarity of one or more lanes is inverted. 

    Can you check the lane parameters mismatch  between framer and deframer using TALISE_getDfrmIlasMismatch API.

    Are you using Default profile ?

    Can you please follow the below steps mentioned in the below post for JESD LINK INITIALIZATION AND DEBUGGING.

     RE: JESD link fail - ADRV9029 

     

  • Hi  ,


               Sorry for the late reply. 

    Excessive intra lane skew. For this can you try using single lane and see if you don't see issue .

       I tried using single lane, at that time also I found the same issues. Our application is to use receiver at 200MHz bandwidth with sampling rate of 245.76Msps and the lane rate is 9.8Gbps.

    Can you check the lane parameters mismatch  between framer and deframer using TALISE_getDfrmIlasMismatch API.

     I have readback the framer and deframer lane parameters using TALISE_getDfrmIlasMismatch() API  and the results are shown below.

    Are you using Default profile ?

     Yes, we are using default profile provided by ADI.

    Can you please follow the below steps mentioned in the below post for JESD LINK INITIALIZATION AND DEBUGGING

     The JESD Initializations wise there is no issues. Only in some power-cycles, noise is coming in receiver data, though input is applied.  Please refer the previously shared query:   RE: ADRV9009 Rx1 and Rx2 Randomly Give Incorrect Data. 

    Please let me know on how to debug this further.

    Thanks and Regards

    Goli Ganesh

  •  I have readback the framer and deframer lane parameters using TALISE_getDfrmIlasMismatch() API  and the results are shown below.

    From the log shared for the ILAS mismatch  for both Chip A and Chip B ,we see few mismatch in the JESD  parameters .

    Can you please check whether the JESD parameters are configured same on both sides . Lane rates , number of lanes and all the JESD configurations should be same for both  FPGA and TRx.

    The issue might be also due to Polarity of one or more lanes is inverted.  Can you please check whether the SERDES lanes are  inverted or not ?

    And hope the SYNC signal status is differential .