KCC's Quizzes AQQ305 about a mutual exponentiation equation
1. Quote of the month: "A train station is where a train stops. A bus station is where a bus stops. I have a work station on my desk, so..." - unknown
2. Quiz AQQ305 about finding a mutual exponential equation
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September Monthly Blog Quiz! Read the blog, take the quiz, and you could win a gift card
Quiz: How Well Do You Know Adaptive Power Switching?
Is your I/O module overheating? The AD74416H's Adaptive Power Switching (APS) can cut heat dissipation by up to 40% — but how well do you really understand how it works?
Read the blog first: Cooling
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ADRV9009
Recommended for New Designs
The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital...
Datasheet
ADRV9009 on Analog.com
AD9528
Recommended for New Designs
The AD9528 is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator for multiple device synchronization. The first stage phase-locked loop...
Datasheet
AD9528 on Analog.com
Hi,
in my application I use 4 chips ADRV9009 that works undependably- not synchronized.
My question is about the signal SYSREF.
According with data sheet this signal used for multi chip synchronization.
I transmit and receive the I and Q in each chip independently. Can I leave this signal disconnected? Or connected to GND?
According with EVB ADRV9009 you connected this signal to PLL AD9528 why?
Thanks
Haim
Yes SYSREF and DEV_CLK should go from the AD9528 clock chip to the ADRV9009 device as well as the FPGA. This helps in achieving baseband synchronization of all the clocks w.r.t to a common REF_CLK that goes as input of the AD9528. So, this step is needed.