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Tx JESD CGS state in ADRV9009 with ZC706



		

			

									
					    Meghraj
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Mar 10, 2023 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Hello team,
    

    We are using ADRV9009 with ZC706 FPGA. Initialization is happening but sometimes we are getting CGS state in Tx JESD.
    

    We did the following test cases:
    

      

    1. Multiple power ons:
      2. 

    

    When we are programming the FPGA after powering on the FPGA multiple times, in some cases we are getting CGS state in Tx JESD link and in some cases we got DATA state.
    

      

    1. Single power on, multiple times programming:
      2. 

    

    We observed that in the first program after powering on the FPGA even if we get CGS state and we programmed the FPGA again and again without powering it off; we get DATA state in Tx JESD from second time onwards.
    

    LOG when we get Tx JESD CGS :
    

    Hello
    

    rx_clkgen: MMCM-PLL locked (122880000 Hz)
    

    tx_clkgen: MMCM-PLL locked (61440000 Hz)
    

    rx_os_clkgen: MMCM-PLL locked (61440000 Hz)
    

    rx_adxcvr: OK (4915200 kHz)
    

    tx_adxcvr: OK (2457600 kHz)
    

    rx_os_adxcvr: OK (2457600 kHz)
    

    warning: TALISE_enableMultichipSync() failed
    

    talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.5
    

    talise: Calibrations completed successfully
    

    warning: TAL_DEFRAMER_A status 0x11
    

    warning: TAL_FRAMER_A status 0x20
    

    warning: TAL_FRAMER_B status 0x28
    

    rx_jesd status:
    

    Link is enabled
    

    Measured Link Clock: 122.882 MHz
    

    Reported Link Clock: 122.880 MHz
    

    Lane rate: 4915.200 MHz
    

    Lane rate / 40: 122.880 MHz
    

    LMFC rate: 3.840 MHz
    

    Link status: DATA
    

    SYSREF captured: No
    

    SYSREF alignment error: No
    

    tx_jesd status:
    

    Link is enabled
    

    Measured Link Clock: 61.441 MHz
    

    Reported Link Clock: 61.440 MHz
    

    Lane rate: 2457.600 MHz
    

    Lane rate / 40: 61.440 MHz
    

    LMFC rate: 3.840 MHz
    

    SYNC~: asserted
    

    Link status: CGS
    

    SYSREF captured: No
    

    SYSREF alignment error: No
    

    rx_os_jesd status:
    

    Link is enabled
    

    Measured Link Clock: 61.441 MHz
    

    Reported Link Clock: 61.440 MHz
    

    Lane rate: 2457.600 MHz
    

    Lane rate / 40: 61.440 MHz
    

    LMFC rate: 3.840 MHz
    

    Link status: DATA
    

    SYSREF captured: No
    

    SYSREF alignment error: No
    

    tx_dac: Successfully initialized (122882080 Hz)
    

    rx_adc: Successfully initialized (122882080 Hz)
    

    

    When we get CGS state in JESD: sync pins are 0 & SYSREF is not getting generated.
    

      
    

    LOG when we get DATA state:
    

    Hello
    

    rx_clkgen: MMCM-PLL locked (122880000 Hz)
    

    tx_clkgen: MMCM-PLL locked (61440000 Hz)
    

    rx_os_clkgen: MMCM-PLL locked (61440000 Hz)
    

    rx_adxcvr: OK (4915200 kHz)
    

    tx_adxcvr: OK (2457600 kHz)
    

    rx_os_adxcvr: OK (2457600 kHz)
    

    talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.5
    

    talise: Calibrations completed successfully
    

    rx_jesd: Lane 0 desynced (9 errors), restarting link
    

    rx_jesd: Lane 1 desynced (77 errors), restarting link
    

    rx_os_jesd: Lane 0 desynced (25 errors), restarting link
    

    rx_os_jesd: Lane 1 desynced (12 errors), restarting link
    

    rx_jesd status:
    

    Link is enabled
    

    Measured Link Clock: 122.882 MHz
    

    Reported Link Clock: 122.880 MHz
    

    Lane rate: 4915.200 MHz
    

    Lane rate / 40: 122.880 MHz
    

    LMFC rate: 3.840 MHz
    

    Link status: DATA
    

    SYSREF captured: Yes
    

    SYSREF alignment error: No
    

    tx_jesd status:
    

    Link is enabled
    

    Measured Link Clock: 61.441 MHz
    

    Reported Link Clock: 61.440 MHz
    

    Lane rate: 2457.600 MHz
    

    Lane rate / 40: 61.440 MHz
    

    LMFC rate: 3.840 MHz
    

    SYNC~: deasserted
    

    Link status: DATA
    

    SYSREF captured: Yes
    

    SYSREF alignment error: No
    

    rx_os_jesd status:
    

    Link is enabled
    

    Measured Link Clock: 61.440 MHz
    

    Reported Link Clock: 61.440 MHz
    

    Lane rate: 2457.600 MHz
    

    Lane rate / 40: 61.440 MHz
    

    LMFC rate: 3.840 MHz
    

    Link status: DATA
    

    SYSREF captured: Yes
    

    SYSREF alignment error: No
    

    tx_dac: Successfully initialized (122882080 Hz)
    

    rx_adc: Successfully initialized (122882080 Hz)
    

     
    

    When we get Tx JESD as data state: we get sync pins as 1 & sysref is getting generated.
    

      
    

    Could you please guide us to resolve this issue?
    

    Thank you in advance.
    

     
    

     
    

     
    

     
    

     
    

     
    

     
    
								
    

				
				
		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	















    
	
    
	
    
					



			








	
	
	
	



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													0
							
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
			                            
                        
                on Mar 13, 2023 7:19 AM
            
            
					
      
	
      

		
		
      
					
      Are you using custom board or eval board?
      

      Are you giving continuous sysref or single shot sysref? What is the framer status and the deframer status?
      

      

      JESD can be struck in CGS phase due to below reasons.
      

      1. Signal integrity issues. I guess this can be ruled out if you are using direct eval board connected to FPGA. Known working hardware.
      

      2. The parameters configured on both sides of FPGA link are different. You can check if all the paramerts configured are same on both sides,
      

      3. Lane rates and number of lanes are different between FPGA and ADRV9009..
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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													0
							
			
				
									
							        
			
			
			
        
            
			                            
                        
                on Mar 17, 2023 6:56 AM
            
            
												
						in reply to srimoyi
					
									
        
	
        

		
		
        
					
        Hello  ,
        Thank you for the response.
        We are actually using evaluation ADRV9009 with custom FPGA. We have tried both continuous sysref and single shot sysref but we get same issue. When we get CGS state the framer deframer status are as below:
        

        warning: TAL_DEFRAMER_A status 0x11
        

        warning: TAL_FRAMER_A status 0x20
        

        warning: TAL_FRAMER_B status 0x28
        


        The JESD parameters have been verified and they seem correct. Number of lanes and lane rates are also correct.
        

        Our main concern is that we are not getting DATA state everytime we poweron the FPGA and program it. We get CGS state sometimes and sometimes we get DATA state . But if we reprogram the FPGA without powering it off , we get DATA state from the second time onwards even if we got CGS state during the first programming. 
        What could be the reason for this and how could we resolve this?
        
			
        

		
		
		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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													0
							
			
				
									
							        
			
			
			
        •  Analog Employees  
        
            
			                            
                        
                on Mar 20, 2023 8:32 AM
            
            
												
						in reply to Meghraj
					
									
        
	
        

		
		
        
					
        Can you check the DEV_CLK that is going to the chip is stable and jitter free?
        

        Also, are you using default profile or are you using the filter wizard to generate profiles? Can you send us the profile that you are using?
        
			
        

		
		
		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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													0
							
			
				
									
							        
			
			
			
          
            
			                            
                        
                on Mar 20, 2023 1:21 PM
            
            
												
						in reply to srimoyi
					
									
          
	
          

		
		
          
					
          Hey Srimoyi, thanks for the response.
          Yes the DEV_CLK is stable and jitter free.
          We are using the below profile from ADI github itself:
          /**
 * \file adrv9009/profiles/tx_bw100_ir122p88_rx_bw100_or122p88_orx_bw100_or122p88_dc122p88/talise_config.c
 * \brief Contains Talise configuration settings for the Talise API
 *
 * Copyright 2015-2017 Analog Devices Inc.
 * Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file.
 *
 * The top level structure taliseDevice_t talDevice uses keyword
 * extern to allow the application layer main() to have visibility
 * to these settings.
 *
 * This file may not be fully complete for the end user application and
 * may need to updated for AGC, GPIO, and DAC full scale settings.
 * To create a full initialisation routine, the user should also refer to the
 * Iron Python initialisation routine generated by the GUI, and also the Talise User Guide.
 *
 */

#include "talise_types.h"
#include "talise_config.h"
#include "talise_error.h"
#include "talise_agc.h"
#ifdef ADI_ZYNQ_PLATFORM
#include "zynq_platform.h"
#endif

int16_t txFirCoefs[80] = {0, 0, 0, 1, 0, -3, 1, 7, -3, -13, 7, 25, -14, -42, 27, 69, -46, -107, 74, 160, -115, -229, 184, 336, -264, -468, 382, 653, -538, -904, 754, 1269, -1056, -1842, 1486, 2879, -2031, -4846, 3816, 16221, 16221, 3816, -4846, -2031, 2879, 1486, -1842, -1056, 1269, 754, -904, -538, 653, 382, -468, -264, 336, 184, -229, -115, 160, 74, -107, -46, 69, 27, -42, -14, 25, 7, -13, -3, 7, 1, -3, 0, 1, 0, 0, 0};

int16_t rxFirCoefs[48] = {-8, -22, 32, 50, -68, -106, 141, 199, -258, -352, 430, 572, -691, -903, 1069, 1392, -1644, -2172, 2569, 3574, -4364, -7129, 9355, 31095, 31095, 9355, -7129, -4364, 3574, 2569, -2172, -1644, 1392, 1069, -903, -691, 572, 430, -352, -258, 199, 141, -106, -68, 50, 32, -22, -8};

int16_t obsrxFirCoefs[48] = {-9, -18, 31, 42, -65, -89, 132, 168, -240, -298, 396, 486, -632, -770, 968, 1163, -1530, -1862, 2369, 3051, -4066, -5983, 9689, 29830, 29830, 9689, -5983, -4066, 3051, 2369, -1862, -1530, 1163, 968, -770, -632, 486, 396, -298, -240, 168, 132, -89, -65, 42, 31, -18, -9};

#ifdef ADI_ZYNQ_PLATFORM /** < Insert Customer Platform HAL State Container here>*/
/*
 * Platform Layer SPI settings - this structure is specific to ADI's platform layer code.
 * User should replace with their own structure or settings for their hardware
 */
zynqSpiSettings_t spiDev1 = {
	.chipSelectIndex = 1,
	.writeBitPolarity = 0,
	.longInstructionWord = 1,
	.CPHA = 0,
	.CPOL = 0,
	.mode = 0,
	.spiClkFreq_Hz = 25000000
};

/*
 * Platform Layer settings - this structure is specific to ADI's platform layer code.
 * User should replace with their own structure or settings for their hardware
 * The structure is held in taliseDevice_t below as a void pointer, allowing
 * the customer to pass any information for their specific hardware down to the
 * hardware layer code.
 */
zynqAdiDev_t talDevHalInfo = {
	.devIndex = 1,
	.spiSettings = &spiDev1,
	.spiErrCode = 0,
	.timerErrCode = 0,
	.gpioErrCode = 0,
	.logLevel = ADIHAL_LOG_ALL
};
#endif
/**
 *  TalDevice a structure used by the Talise API to hold the platform hardware
 *  structure information, as well as an internal Talise API state container
 *  (devStateInfo) of runtime information used by the API.
 **/
taliseDevice_t talDevice = {
#ifdef ADI_ZYNQ_PLATFORM
	/* Void pointer of users platform HAL settings to pass to HAL layer calls
	 * Talise API does not use the devHalInfo member */
	.devHalInfo = &talDevHalInfo,
#else
	.devHalInfo = NULL,     /* < Insert Customer Platform HAL State Container here>*/
#endif
	/* devStateInfo is maintained internal to the Talise API, just create the memory */
	.devStateInfo = {0}

};

taliseInit_t talInit = {
	/* SPI settings */
	.spiSettings =
	{
		.MSBFirst            = 1,  /* 1 = MSBFirst, 0 = LSBFirst */
		.enSpiStreaming      = 0,  /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
		.autoIncAddrUp       = 1,  /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
		.fourWireMode        = 1,  /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
		.cmosPadDrvStrength  = TAL_CMOSPAD_DRV_2X /* Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */
	},

	/* Rx settings */
	.rx =
	{
		.rxProfile =
		{
			.rxFir =
			{
				.gain_dB = -6,                /* filter gain */
				.numFirCoefs = 48,            /* number of coefficients in the FIR filter */
				.coefs = &rxFirCoefs[0]
			},
			.rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
			.rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
			.rhb1Decimation = 2,            /* RX Half band 1 decimation (1 or 2) */
			.rxOutputRate_kHz = 122880,            /* Rx IQ data rate in kHz */
			.rfBandwidth_Hz = 100000000,    /* The Rx RF passband bandwidth for the profile */
			.rxBbf3dBCorner_kHz = 100000,    /* Rx BBF 3dB corner in kHz */
			.rxAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},            /* pointer to custom ADC profile */
			.rxDdcMode = TAL_RXDDC_BYPASS,   /* Rx DDC mode */
			.rxNcoShifterCfg =
			{
				.bandAInputBandWidth_kHz = 0,
				.bandAInputCenterFreq_kHz = 0,
				.bandANco1Freq_kHz = 0,
				.bandANco2Freq_kHz = 0,
				.bandBInputBandWidth_kHz = 0,
				.bandBInputCenterFreq_kHz = 0,
				.bandBNco1Freq_kHz = 0,
				.bandBNco2Freq_kHz = 0
			}
		},
		.framerSel = TAL_FRAMER_A,            /* Rx JESD204b framer configuration */
		.rxGainCtrl =
		{
			.gainMode = TAL_MGC,            /* taliserxGainMode_t gainMode */
			.rx1GainIndex = 255,            /* uint8_t rx1GainIndex */
			.rx2GainIndex = 255,            /* uint8_t rx2GainIndex */
			.rx1MaxGainIndex = 255,            /* uint8_t rx1MaxGainIndex */
			.rx1MinGainIndex = 195,            /* uint8_t rx1MinGainIndex */
			.rx2MaxGainIndex = 255,            /* uint8_t rx2MaxGainIndex */
			.rx2MinGainIndex = 195            /* uint8_t rx2MinGainIndex */
		},
		.rxChannels = TAL_RX1RX2,                /* The desired Rx Channels to enable during initialization */
	},


	/* Tx settings */
	.tx =
	{
		.txProfile =
		{
			.dacDiv = 1,                        /* The divider used to generate the DAC clock */
			.txFir =
			{
				.gain_dB = 6,                        /* filter gain */
				.numFirCoefs = 80,                    /* number of coefficients in the FIR filter */
				.coefs = &txFirCoefs[0]
			},
			.txFirInterpolation = 2,                    /* The Tx digital FIR filter interpolation (1,2,4) */
			.thb1Interpolation = 2,                    /* Tx Halfband1 filter interpolation (1,2) */
			.thb2Interpolation = 2,                    /* Tx Halfband2 filter interpolation (1,2)*/
			.thb3Interpolation = 2,                    /* Tx Halfband3 filter interpolation (1,2)*/
			.txInt5Interpolation = 1,                    /* Tx Int5 filter interpolation (1,5) */
			.txInputRate_kHz = 122880,                    /* Primary Signal BW */
			.primarySigBandwidth_Hz = 50000000,    /* The Rx RF passband bandwidth for the profile */
			.rfBandwidth_Hz = 100000000,            /* The Tx RF passband bandwidth for the profile */
			.txDac3dBCorner_kHz = 187000,                /* The DAC filter 3dB corner in kHz */
			.txBbf3dBCorner_kHz = 56000,                /* The BBF 3dB corner in kHz */
			.loopBackAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905}
		},
		.deframerSel = TAL_DEFRAMER_A,                    /* Talise JESD204b deframer config for the Tx data path */
		.txChannels = TAL_TX1TX2,                            /* The desired Tx channels to enable during initialization */
		.txAttenStepSize = TAL_TXATTEN_0P05_DB,            /* Tx Attenuation step size */
		.tx1Atten_mdB = 10000,                            /* Initial Tx1 Attenuation */
		.tx2Atten_mdB = 10000,                            /* Initial Tx2 Attenuation */
		.disTxDataIfPllUnlock = TAL_TXDIS_TX_RAMP_DOWN_TO_ZERO    /* Options to disable the transmit data when the RFPLL unlocks. */
	},


	/* ObsRx settings */
	.obsRx =
	{
		.orxProfile =
		{
			.rxFir =
			{
				.gain_dB = 6,                /* filter gain */
				.numFirCoefs = 48,            /* number of coefficients in the FIR filter */
				.coefs = &obsrxFirCoefs[0]
			},
			.rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
			.rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
			.rhb1Decimation = 2,            /* RX Half band 1 decimation (1 or 2) */
			.orxOutputRate_kHz = 122880,            /* Rx IQ data rate in kHz */
			.rfBandwidth_Hz = 100000000,    /* The Rx RF passband bandwidth for the profile */
			.rxBbf3dBCorner_kHz = 225000,    /* Rx BBF 3dB corner in kHz */
			.orxLowPassAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},
			.orxBandPassAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},
			.orxDdcMode = TAL_ORXDDC_DISABLED,   /* ORx DDC mode */
			.orxMergeFilter  = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
		},
		.orxGainCtrl =
		{
			.gainMode = TAL_MGC,
			.orx1GainIndex = 255,
			.orx2GainIndex = 255,
			.orx1MaxGainIndex = 255,
			.orx1MinGainIndex = 195,
			.orx2MaxGainIndex = 255,
			.orx2MinGainIndex = 195
		},
		.framerSel = TAL_FRAMER_B,                /* ObsRx JESD204b framer configuration */
		.obsRxChannelsEnable = TAL_ORX1ORX2,        /* The desired ObsRx Channels to enable during initialization */
		.obsRxLoSource = TAL_OBSLO_RF_PLL                /* The ORx mixers can use the TX_PLL */
	},

	/* Digital Clock Settings */
	.clocks =
	{
		.deviceClock_kHz = 122880,            /* CLKPLL and device reference clock frequency in kHz */
		.clkPllVcoFreq_kHz = 9830400,        /* CLKPLL VCO frequency in kHz */
		.clkPllHsDiv = TAL_HSDIV_2P5,            /* CLKPLL high speed clock divider */
		.rfPllUseExternalLo = 0,                /* 1= Use external LO for RF PLL, 0 = use internal LO generation for RF PLL */
		.rfPllPhaseSyncMode = TAL_RFPLLMCS_NOSYNC                /* RFPLL MCS (Phase sync) mode */
	},

	/* JESD204B settings */
	.jesd204Settings =
	{
		/* Framer A settings */
		.framerA =
		{
			.bankId = 1,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
			.M = 4,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
			.K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
			.F = 4,                            /* F (number of bytes per frame) */
			.Np = 16,                            /* Np (converter sample resolution) */
			.scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
			.externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
			.serializerLanesEnabled = 0x03,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
			.serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
			.lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbInSelect = 0,                /* syncbInSelect; */
			.overSample = 0,                    /* 1=overSample, 0=bitRepeat */
			.syncbInLvdsMode = 1,
			.syncbInLvdsPnInvert = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		/* Framer B settings */
		.framerB =
		{
			.bankId = 0,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
			.M = 2,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
			.K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
			.F = 2,                            /* F (number of bytes per frame) */
			.Np = 16,                            /* Np (converter sample resolution) */
			.scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
			.externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
			.serializerLanesEnabled = 0x0C,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
			.serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
			.lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbInSelect = 1,                /* syncbInSelect; */
			.overSample = 0,                    /* 1=overSample, 0=bitRepeat */
			.syncbInLvdsMode = 1,
			.syncbInLvdsPnInvert = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		/* Deframer A settings */
		.deframerA =
		{
			.bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
			.M = 4,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
			.K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
			.scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
			.externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
			.deserializerLanesEnabled = 0x0F,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
			.deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
			.lmfcOffset = 17,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbOutSelect = 0,                /* SYNCBOUT0/1 select */
			.Np = 16,                /* Np (converter sample resolution) */
			.syncbOutLvdsMode = 1,
			.syncbOutLvdsPnInvert = 0,
			.syncbOutCmosSlewRate = 0,
			.syncbOutCmosDriveLevel = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		/* Deframer B settings */
		.deframerB =
		{
			.bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
			.M = 0,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
			.K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
			.scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
			.externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
			.deserializerLanesEnabled = 0x00,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
			.deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
			.lmfcOffset = 0,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbOutSelect = 1,                /* SYNCBOUT0/1 select */
			.Np = 16,                /* Np (converter sample resolution) */
			.syncbOutLvdsMode = 1,
			.syncbOutLvdsPnInvert = 0,
			.syncbOutCmosSlewRate = 0,
			.syncbOutCmosDriveLevel = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		.serAmplitude = 15,                    /* Serializer amplitude setting. Default = 15. Range is 0..15 */
		.serPreEmphasis = 1,                /* Serializer pre-emphasis setting. Default = 1 Range is 0..4 */
		.serInvertLanePolarity = 0,            /* Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */
		.desInvertLanePolarity = 0,            /* Deserializer Lane PN inversion select.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */
		.desEqSetting = 1,                    /* Deserializer Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */
		.sysrefLvdsMode = 1,                /* Use LVDS inputs on Talise for SYSREF */
		.sysrefLvdsPnInvert = 0              /*0= Do not PN invert SYSREF */
	}
};

//Only needs to be called if user wants to setup AGC parameters
static taliseAgcCfg_t rxAgcCtrl = {
	4,
	255,
	195,
	255,
	195,
	30720,  /* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 245.76 Mhz) */
	10,
	10,
	16,
	0,
	1,
	0,
	0,
	0,
	1,
	31,
	246,
	4,
	1,          /*!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */
	/* agcPower */
	{
		1,      /*!<1-bit field, enables the Rx power measurement block. */
		1,      /*!<1-bit field, allows using Rx PFIR for power measurement. */
		0,      /*!<1-bit field, allows to use the output of the second digital offset block in the Rx datapath for power measurement. */
		9,      /*!<AGC power measurement detect lower 0 threshold. Default = -12dBFS == 5, 7-bit register value where max = 0x7F, min = 0x00 */
		2,      /*!<AGC power measurement detect lower 1 threshold. Default = (offset) 4dB == 0, 4-bit register value where  max = 0xF, min = 0x00 */
		4,      /*!<AGC power measurement detect lower 0 recovery gain step. Default = 2dB - based on gain table step  size, 5-bit register value where max = 0x1F, min = 0x00 */
		4,      /*!<AGC power measurement detect lower 1 recovery gain step. Default = 4dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
		5,      /*!< power measurement duration used by the decimated power block. Default = 0x05, 5-bit register value where max = 0x1F, min = 0x00 */
		5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		2,      /*!<Default value should be 2*/
		0,
		0
	},
	/* agcPeak */
	{
		205,        /*!<1st update interval for the multiple time constant in AGC loop mode, Default:205. */
		2,          /*!<sets the 2nd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of  agcUnderRangeLowInterval  , Default: 4 */
		4,          /*!<sets the 3rd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeMidInterval and agcUnderRangeLowInterval, Default: 4 */
		39,         /*!<AGC APD high threshold. Default=0x1F, 6-bit register value where max=0x3F, min =0x00 */
		49,         /*!<AGC APD peak detect high threshold. default = 0x1F, 6-bit register value where max = 0x3F, min = 0x00.  Set to 3dB below apdHighThresh */
		23,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max =0x3F, min = 0x00 */
		19,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max = 0x3F, min = 0x00 . Set to 3dB below apdLowThresh  */
		6,          /*!<AGC APD peak detect upper threshold count. Default = 0x06 8-bit register value where max = 0xFF, min = 0x20  */
		3,          /*!<AGC APD peak detect lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00  */
		4,          /*!<AGC APD peak detect attack gain step. Default = 2dB step - based on gain table step size, 5-bit register  value, where max = 0x1F, min = 0x00  */
		2,          /*!<AGC APD gain index step size. Recommended to be same as hb2GainStepRecovery. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00  */
		1,          /*!<1-bit field, enables or disables the HB2 overload detector.  */
		1,          /*!<3-bit field. Sets the window of clock cycles (at the HB2 output rate) to meet the overload count. */
		1,          /*!<4-bit field. Sets the number of actual overloads required to trigger the overload signal.  */
		181,        /*!<AGC decimator output high threshold. Default = 0xB5, 8-bit register value where max = 0xFF, min = 0x00 */
		45,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
		90,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
		128,        /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
		6,          /*!<AGC HB2 output upper threshold count. Default = 0x06, 8-bit register value where max = 0xFF, min =  0x20 */
		3,          /*!<AGC HB2 output lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
		2,          /*!<AGC decimator gain index step size. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
		4,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 0 triggers a programmable number  of times. Default = 0x08, 5-bit register value where max = 0x1F, min = 0x00 */
		8,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 1 triggers a programmable number of times. Default = 0x04, 5-bit register value where max = 0x1F, min = 0x00 */
		4,          /*!<AGC decimator output attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
		1,
		0,
		0
	}
};
          
			
          

		
		
		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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													0
							
			
				
									
							        
			
			
			
            
            
			                            
                        
                on Mar 20, 2023 1:25 PM
            
            
												
						in reply to srimoyi
					
									
            
	
            

		
		
            
					
            Hello Srimoyi,
            

            The DEV_CLK is stable and jitter free. 
            We are using the below profile from ADI itself:
            /**
 * \file adrv9009/profiles/tx_bw100_ir122p88_rx_bw100_or122p88_orx_bw100_or122p88_dc122p88/talise_config.c
 * \brief Contains Talise configuration settings for the Talise API
 *
 * Copyright 2015-2017 Analog Devices Inc.
 * Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file.
 *
 * The top level structure taliseDevice_t talDevice uses keyword
 * extern to allow the application layer main() to have visibility
 * to these settings.
 *
 * This file may not be fully complete for the end user application and
 * may need to updated for AGC, GPIO, and DAC full scale settings.
 * To create a full initialisation routine, the user should also refer to the
 * Iron Python initialisation routine generated by the GUI, and also the Talise User Guide.
 *
 */

#include "talise_types.h"
#include "talise_config.h"
#include "talise_error.h"
#include "talise_agc.h"
#ifdef ADI_ZYNQ_PLATFORM
#include "zynq_platform.h"
#endif

int16_t txFirCoefs[80] = {0, 0, 0, 1, 0, -3, 1, 7, -3, -13, 7, 25, -14, -42, 27, 69, -46, -107, 74, 160, -115, -229, 184, 336, -264, -468, 382, 653, -538, -904, 754, 1269, -1056, -1842, 1486, 2879, -2031, -4846, 3816, 16221, 16221, 3816, -4846, -2031, 2879, 1486, -1842, -1056, 1269, 754, -904, -538, 653, 382, -468, -264, 336, 184, -229, -115, 160, 74, -107, -46, 69, 27, -42, -14, 25, 7, -13, -3, 7, 1, -3, 0, 1, 0, 0, 0};

int16_t rxFirCoefs[48] = {-8, -22, 32, 50, -68, -106, 141, 199, -258, -352, 430, 572, -691, -903, 1069, 1392, -1644, -2172, 2569, 3574, -4364, -7129, 9355, 31095, 31095, 9355, -7129, -4364, 3574, 2569, -2172, -1644, 1392, 1069, -903, -691, 572, 430, -352, -258, 199, 141, -106, -68, 50, 32, -22, -8};

int16_t obsrxFirCoefs[48] = {-9, -18, 31, 42, -65, -89, 132, 168, -240, -298, 396, 486, -632, -770, 968, 1163, -1530, -1862, 2369, 3051, -4066, -5983, 9689, 29830, 29830, 9689, -5983, -4066, 3051, 2369, -1862, -1530, 1163, 968, -770, -632, 486, 396, -298, -240, 168, 132, -89, -65, 42, 31, -18, -9};

#ifdef ADI_ZYNQ_PLATFORM /** < Insert Customer Platform HAL State Container here>*/
/*
 * Platform Layer SPI settings - this structure is specific to ADI's platform layer code.
 * User should replace with their own structure or settings for their hardware
 */
zynqSpiSettings_t spiDev1 = {
	.chipSelectIndex = 1,
	.writeBitPolarity = 0,
	.longInstructionWord = 1,
	.CPHA = 0,
	.CPOL = 0,
	.mode = 0,
	.spiClkFreq_Hz = 25000000
};

/*
 * Platform Layer settings - this structure is specific to ADI's platform layer code.
 * User should replace with their own structure or settings for their hardware
 * The structure is held in taliseDevice_t below as a void pointer, allowing
 * the customer to pass any information for their specific hardware down to the
 * hardware layer code.
 */
zynqAdiDev_t talDevHalInfo = {
	.devIndex = 1,
	.spiSettings = &spiDev1,
	.spiErrCode = 0,
	.timerErrCode = 0,
	.gpioErrCode = 0,
	.logLevel = ADIHAL_LOG_ALL
};
#endif
/**
 *  TalDevice a structure used by the Talise API to hold the platform hardware
 *  structure information, as well as an internal Talise API state container
 *  (devStateInfo) of runtime information used by the API.
 **/
taliseDevice_t talDevice = {
#ifdef ADI_ZYNQ_PLATFORM
	/* Void pointer of users platform HAL settings to pass to HAL layer calls
	 * Talise API does not use the devHalInfo member */
	.devHalInfo = &talDevHalInfo,
#else
	.devHalInfo = NULL,     /* < Insert Customer Platform HAL State Container here>*/
#endif
	/* devStateInfo is maintained internal to the Talise API, just create the memory */
	.devStateInfo = {0}

};

taliseInit_t talInit = {
	/* SPI settings */
	.spiSettings =
	{
		.MSBFirst            = 1,  /* 1 = MSBFirst, 0 = LSBFirst */
		.enSpiStreaming      = 0,  /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
		.autoIncAddrUp       = 1,  /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
		.fourWireMode        = 1,  /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
		.cmosPadDrvStrength  = TAL_CMOSPAD_DRV_2X /* Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */
	},

	/* Rx settings */
	.rx =
	{
		.rxProfile =
		{
			.rxFir =
			{
				.gain_dB = -6,                /* filter gain */
				.numFirCoefs = 48,            /* number of coefficients in the FIR filter */
				.coefs = &rxFirCoefs[0]
			},
			.rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
			.rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
			.rhb1Decimation = 2,            /* RX Half band 1 decimation (1 or 2) */
			.rxOutputRate_kHz = 122880,            /* Rx IQ data rate in kHz */
			.rfBandwidth_Hz = 100000000,    /* The Rx RF passband bandwidth for the profile */
			.rxBbf3dBCorner_kHz = 100000,    /* Rx BBF 3dB corner in kHz */
			.rxAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},            /* pointer to custom ADC profile */
			.rxDdcMode = TAL_RXDDC_BYPASS,   /* Rx DDC mode */
			.rxNcoShifterCfg =
			{
				.bandAInputBandWidth_kHz = 0,
				.bandAInputCenterFreq_kHz = 0,
				.bandANco1Freq_kHz = 0,
				.bandANco2Freq_kHz = 0,
				.bandBInputBandWidth_kHz = 0,
				.bandBInputCenterFreq_kHz = 0,
				.bandBNco1Freq_kHz = 0,
				.bandBNco2Freq_kHz = 0
			}
		},
		.framerSel = TAL_FRAMER_A,            /* Rx JESD204b framer configuration */
		.rxGainCtrl =
		{
			.gainMode = TAL_MGC,            /* taliserxGainMode_t gainMode */
			.rx1GainIndex = 255,            /* uint8_t rx1GainIndex */
			.rx2GainIndex = 255,            /* uint8_t rx2GainIndex */
			.rx1MaxGainIndex = 255,            /* uint8_t rx1MaxGainIndex */
			.rx1MinGainIndex = 195,            /* uint8_t rx1MinGainIndex */
			.rx2MaxGainIndex = 255,            /* uint8_t rx2MaxGainIndex */
			.rx2MinGainIndex = 195            /* uint8_t rx2MinGainIndex */
		},
		.rxChannels = TAL_RX1RX2,                /* The desired Rx Channels to enable during initialization */
	},


	/* Tx settings */
	.tx =
	{
		.txProfile =
		{
			.dacDiv = 1,                        /* The divider used to generate the DAC clock */
			.txFir =
			{
				.gain_dB = 6,                        /* filter gain */
				.numFirCoefs = 80,                    /* number of coefficients in the FIR filter */
				.coefs = &txFirCoefs[0]
			},
			.txFirInterpolation = 2,                    /* The Tx digital FIR filter interpolation (1,2,4) */
			.thb1Interpolation = 2,                    /* Tx Halfband1 filter interpolation (1,2) */
			.thb2Interpolation = 2,                    /* Tx Halfband2 filter interpolation (1,2)*/
			.thb3Interpolation = 2,                    /* Tx Halfband3 filter interpolation (1,2)*/
			.txInt5Interpolation = 1,                    /* Tx Int5 filter interpolation (1,5) */
			.txInputRate_kHz = 122880,                    /* Primary Signal BW */
			.primarySigBandwidth_Hz = 50000000,    /* The Rx RF passband bandwidth for the profile */
			.rfBandwidth_Hz = 100000000,            /* The Tx RF passband bandwidth for the profile */
			.txDac3dBCorner_kHz = 187000,                /* The DAC filter 3dB corner in kHz */
			.txBbf3dBCorner_kHz = 56000,                /* The BBF 3dB corner in kHz */
			.loopBackAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905}
		},
		.deframerSel = TAL_DEFRAMER_A,                    /* Talise JESD204b deframer config for the Tx data path */
		.txChannels = TAL_TX1TX2,                            /* The desired Tx channels to enable during initialization */
		.txAttenStepSize = TAL_TXATTEN_0P05_DB,            /* Tx Attenuation step size */
		.tx1Atten_mdB = 10000,                            /* Initial Tx1 Attenuation */
		.tx2Atten_mdB = 10000,                            /* Initial Tx2 Attenuation */
		.disTxDataIfPllUnlock = TAL_TXDIS_TX_RAMP_DOWN_TO_ZERO    /* Options to disable the transmit data when the RFPLL unlocks. */
	},


	/* ObsRx settings */
	.obsRx =
	{
		.orxProfile =
		{
			.rxFir =
			{
				.gain_dB = 6,                /* filter gain */
				.numFirCoefs = 48,            /* number of coefficients in the FIR filter */
				.coefs = &obsrxFirCoefs[0]
			},
			.rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
			.rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
			.rhb1Decimation = 2,            /* RX Half band 1 decimation (1 or 2) */
			.orxOutputRate_kHz = 122880,            /* Rx IQ data rate in kHz */
			.rfBandwidth_Hz = 100000000,    /* The Rx RF passband bandwidth for the profile */
			.rxBbf3dBCorner_kHz = 225000,    /* Rx BBF 3dB corner in kHz */
			.orxLowPassAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},
			.orxBandPassAdcProfile = {265, 146, 181, 90, 1280, 366, 1257, 27, 1258, 17, 718, 39, 48, 46, 27, 161, 0, 0, 0, 0, 40, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},
			.orxDdcMode = TAL_ORXDDC_DISABLED,   /* ORx DDC mode */
			.orxMergeFilter  = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
		},
		.orxGainCtrl =
		{
			.gainMode = TAL_MGC,
			.orx1GainIndex = 255,
			.orx2GainIndex = 255,
			.orx1MaxGainIndex = 255,
			.orx1MinGainIndex = 195,
			.orx2MaxGainIndex = 255,
			.orx2MinGainIndex = 195
		},
		.framerSel = TAL_FRAMER_B,                /* ObsRx JESD204b framer configuration */
		.obsRxChannelsEnable = TAL_ORX1ORX2,        /* The desired ObsRx Channels to enable during initialization */
		.obsRxLoSource = TAL_OBSLO_RF_PLL                /* The ORx mixers can use the TX_PLL */
	},

	/* Digital Clock Settings */
	.clocks =
	{
		.deviceClock_kHz = 122880,            /* CLKPLL and device reference clock frequency in kHz */
		.clkPllVcoFreq_kHz = 9830400,        /* CLKPLL VCO frequency in kHz */
		.clkPllHsDiv = TAL_HSDIV_2P5,            /* CLKPLL high speed clock divider */
		.rfPllUseExternalLo = 0,                /* 1= Use external LO for RF PLL, 0 = use internal LO generation for RF PLL */
		.rfPllPhaseSyncMode = TAL_RFPLLMCS_NOSYNC                /* RFPLL MCS (Phase sync) mode */
	},

	/* JESD204B settings */
	.jesd204Settings =
	{
		/* Framer A settings */
		.framerA =
		{
			.bankId = 1,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
			.M = 4,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
			.K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
			.F = 4,                            /* F (number of bytes per frame) */
			.Np = 16,                            /* Np (converter sample resolution) */
			.scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
			.externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
			.serializerLanesEnabled = 0x03,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
			.serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
			.lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbInSelect = 0,                /* syncbInSelect; */
			.overSample = 0,                    /* 1=overSample, 0=bitRepeat */
			.syncbInLvdsMode = 1,
			.syncbInLvdsPnInvert = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		/* Framer B settings */
		.framerB =
		{
			.bankId = 0,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
			.M = 2,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
			.K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
			.F = 2,                            /* F (number of bytes per frame) */
			.Np = 16,                            /* Np (converter sample resolution) */
			.scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
			.externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
			.serializerLanesEnabled = 0x0C,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
			.serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
			.lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbInSelect = 1,                /* syncbInSelect; */
			.overSample = 0,                    /* 1=overSample, 0=bitRepeat */
			.syncbInLvdsMode = 1,
			.syncbInLvdsPnInvert = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		/* Deframer A settings */
		.deframerA =
		{
			.bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
			.M = 4,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
			.K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
			.scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
			.externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
			.deserializerLanesEnabled = 0x0F,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
			.deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
			.lmfcOffset = 17,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbOutSelect = 0,                /* SYNCBOUT0/1 select */
			.Np = 16,                /* Np (converter sample resolution) */
			.syncbOutLvdsMode = 1,
			.syncbOutLvdsPnInvert = 0,
			.syncbOutCmosSlewRate = 0,
			.syncbOutCmosDriveLevel = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		/* Deframer B settings */
		.deframerB =
		{
			.bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
			.M = 0,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
			.K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
			.scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
			.externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
			.deserializerLanesEnabled = 0x00,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
			.deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
			.lmfcOffset = 0,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbOutSelect = 1,                /* SYNCBOUT0/1 select */
			.Np = 16,                /* Np (converter sample resolution) */
			.syncbOutLvdsMode = 1,
			.syncbOutLvdsPnInvert = 0,
			.syncbOutCmosSlewRate = 0,
			.syncbOutCmosDriveLevel = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		.serAmplitude = 15,                    /* Serializer amplitude setting. Default = 15. Range is 0..15 */
		.serPreEmphasis = 1,                /* Serializer pre-emphasis setting. Default = 1 Range is 0..4 */
		.serInvertLanePolarity = 0,            /* Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */
		.desInvertLanePolarity = 0,            /* Deserializer Lane PN inversion select.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */
		.desEqSetting = 1,                    /* Deserializer Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */
		.sysrefLvdsMode = 1,                /* Use LVDS inputs on Talise for SYSREF */
		.sysrefLvdsPnInvert = 0              /*0= Do not PN invert SYSREF */
	}
};

//Only needs to be called if user wants to setup AGC parameters
static taliseAgcCfg_t rxAgcCtrl = {
	4,
	255,
	195,
	255,
	195,
	30720,  /* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 245.76 Mhz) */
	10,
	10,
	16,
	0,
	1,
	0,
	0,
	0,
	1,
	31,
	246,
	4,
	1,          /*!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */
	/* agcPower */
	{
		1,      /*!<1-bit field, enables the Rx power measurement block. */
		1,      /*!<1-bit field, allows using Rx PFIR for power measurement. */
		0,      /*!<1-bit field, allows to use the output of the second digital offset block in the Rx datapath for power measurement. */
		9,      /*!<AGC power measurement detect lower 0 threshold. Default = -12dBFS == 5, 7-bit register value where max = 0x7F, min = 0x00 */
		2,      /*!<AGC power measurement detect lower 1 threshold. Default = (offset) 4dB == 0, 4-bit register value where  max = 0xF, min = 0x00 */
		4,      /*!<AGC power measurement detect lower 0 recovery gain step. Default = 2dB - based on gain table step  size, 5-bit register value where max = 0x1F, min = 0x00 */
		4,      /*!<AGC power measurement detect lower 1 recovery gain step. Default = 4dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
		5,      /*!< power measurement duration used by the decimated power block. Default = 0x05, 5-bit register value where max = 0x1F, min = 0x00 */
		5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		2,      /*!<Default value should be 2*/
		0,
		0
	},
	/* agcPeak */
	{
		205,        /*!<1st update interval for the multiple time constant in AGC loop mode, Default:205. */
		2,          /*!<sets the 2nd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of  agcUnderRangeLowInterval  , Default: 4 */
		4,          /*!<sets the 3rd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeMidInterval and agcUnderRangeLowInterval, Default: 4 */
		39,         /*!<AGC APD high threshold. Default=0x1F, 6-bit register value where max=0x3F, min =0x00 */
		49,         /*!<AGC APD peak detect high threshold. default = 0x1F, 6-bit register value where max = 0x3F, min = 0x00.  Set to 3dB below apdHighThresh */
		23,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max =0x3F, min = 0x00 */
		19,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max = 0x3F, min = 0x00 . Set to 3dB below apdLowThresh  */
		6,          /*!<AGC APD peak detect upper threshold count. Default = 0x06 8-bit register value where max = 0xFF, min = 0x20  */
		3,          /*!<AGC APD peak detect lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00  */
		4,          /*!<AGC APD peak detect attack gain step. Default = 2dB step - based on gain table step size, 5-bit register  value, where max = 0x1F, min = 0x00  */
		2,          /*!<AGC APD gain index step size. Recommended to be same as hb2GainStepRecovery. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00  */
		1,          /*!<1-bit field, enables or disables the HB2 overload detector.  */
		1,          /*!<3-bit field. Sets the window of clock cycles (at the HB2 output rate) to meet the overload count. */
		1,          /*!<4-bit field. Sets the number of actual overloads required to trigger the overload signal.  */
		181,        /*!<AGC decimator output high threshold. Default = 0xB5, 8-bit register value where max = 0xFF, min = 0x00 */
		45,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
		90,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
		128,        /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
		6,          /*!<AGC HB2 output upper threshold count. Default = 0x06, 8-bit register value where max = 0xFF, min =  0x20 */
		3,          /*!<AGC HB2 output lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
		2,          /*!<AGC decimator gain index step size. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
		4,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 0 triggers a programmable number  of times. Default = 0x08, 5-bit register value where max = 0x1F, min = 0x00 */
		8,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 1 triggers a programmable number of times. Default = 0x04, 5-bit register value where max = 0x1F, min = 0x00 */
		4,          /*!<AGC decimator output attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
		1,
		0,
		0
	}
};
            
			
            

		
		
		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
						
				
						
				
				
		
		
            
			
		
            
	
            

            

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													0
							
			
				
									
							        
			
			
			
              
            
			                            
                        
                on Mar 24, 2023 5:25 PM
            
            
												
						in reply to srimoyi
					
									
              
	
              

		
		
              
					
              Hello  , we tried lowering the lane rates but still we are facing the same issue. We also tried changing xcvr paramters according to the above link but still we see CGS state on some power ons. Please suggest what could we further do to resolve this issue? 
              
			
              

		
		
		
		
	
              
	
              
		
              
			
		
              
	
              
	
              
		
						
						
				
						
				
				
		
		
              
			
		
              
	
              

              

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													0
							
			
				
									
							        
			
			
			
              •  Analog Employees  
              
            
			                            
                        
                on Mar 27, 2023 10:05 AM
            
            
												
						in reply to Meghraj
					
									
              
	
              

		
		
              
					
              Can you try with the attached profile? 
              

               



              
    
              
        Fullscreen
        Tx_BW50_IR61p44_Rx_BW50_OR61p44_ORx_BW50_OR61p44.txt
        Download
    
              
    
              <profile Talise version=1 name=Tx_BW50_IR61p44_Rx_BW50_OR61p44_ORx_BW50_OR61p44>
 <clocks>
  <deviceClock_kHz=122880>
  <clkPllVcoFreq_kHz=9830400>
  <clkPllHsDiv=2.5>
 </clocks>

 <rx name=Rx 50.00MHz, OutputRate 61.44MHz, TotalDecimation 32>
  <rxChannels=TAL_RX1RX2>
  <rxFirDecimation=4>
  <rxDec5Decimation=4>
  <rhb1Decimation=2>
  <rxOutputRate_kHz=61440>
  <rfBandwidth_Hz=50000000>
  <rxBbf3dBCorner_kHz=50000>
  <rxDdcMode=0>

  <rxNcoShifterCfg>
   <bandAInputBandWidth_kHz=0>
   <bandAInputCenterFreq_kHz=0>
   <bandANco1Freq_kHz=0>
   <bandANco2Freq_kHz=0>
   <bandBInputBandWidth_kHz=0>
   <bandBInputCenterFreq_kHz=0>
   <bandBNco1Freq_kHz=0>
   <bandBNco2Freq_kHz=0>
  </rxNcoShifterCfg>

  <filter FIR gain_dB=-6 numFirCoefs=72>
  -26
  89
  47
  39
  -40
  -104
  -137
  -65
  71
  221
  254
  130
  -140
  -388
  -454
  -216
  232
  659
  751
  365
  -381
  -1069
  -1231
  -604
  603
  1755
  2060
  1060
  -1008
  -3146
  -3975
  -2381
  1838
  7716
  13398
  16883
  16883
  13398
  7716
  1838
  -2381
  -3975
  -3146
  -1008
  1060
  2060
  1755
  603
  -604
  -1231
  -1069
  -381
  365
  751
  659
  232
  -216
  -454
  -388
  -140
  130
  254
  221
  71
  -65
  -137
  -104
  -40
  39
  47
  89
  -26
  </filter>

  <rxAdcProfile num=42>
  265
  146
  181
  90
  1280
  366
  1257
  27
  1258
  17
  718
  39
  48
  46
  27
  161
  0
  0
  0
  0
  40
  0
  7
  6
  42
  0
  7
  6
  42
  0
  25
  27
  0
  0
  25
  27
  0
  0
  165
  44
  31
  905
  </rxAdcProfile>
 </rx>

 <obsRx name=Rx 50.00MHz, OutputRate 61.44MHz, TotalDecimation 32>
  <obsRxChannelsEnable=TAL_ORX1ORX2>
  <enAdcStitching=0>
  <rxFirDecimation=4>
  <rxDec5Decimation=4>
  <rhb1Decimation=2>
  <orxOutputRate_kHz=61440>
  <rfBandwidth_Hz=50000000>
  <rxBbf3dBCorner_kHz=225000>
  <orxDdcMode=0>

  <filter FIR gain_dB=-12 numFirCoefs=72>
  -8
  126
  92
  46
  -78
  -189
  -223
  -92
  149
  387
  425
  185
  -275
  -685
  -757
  -322
  457
  1155
  1262
  549
  -737
  -1878
  -2072
  -922
  1170
  3076
  3455
  1580
  -2049
  -5623
  -6715
  -3424
  4523
  15336
  25683
  31998
  31998
  25683
  15336
  4523
  -3424
  -6715
  -5623
  -2049
  1580
  3455
  3076
  1170
  -922
  -2072
  -1878
  -737
  549
  1262
  1155
  457
  -322
  -757
  -685
  -275
  185
  425
  387
  149
  -92
  -223
  -189
  -78
  46
  92
  126
  -8
  </filter>

  <orxLowPassAdcProfile num=42>
  265
  146
  181
  90
  1280
  366
  1257
  27
  1258
  17
  718
  39
  48
  46
  27
  161
  0
  0
  0
  0
  40
  0
  7
  6
  42
  0
  7
  6
  42
  0
  25
  27
  0
  0
  25
  27
  0
  0
  165
  44
  31
  905
  </orxLowPassAdcProfile>

  <orxBandPassAdcProfile num=42>
  265
  146
  181
  90
  1280
  366
  1257
  27
  1258
  17
  718
  39
  48
  46
  27
  161
  0
  0
  0
  0
  40
  0
  7
  6
  42
  0
  7
  6
  42
  0
  25
  27
  0
  0
  25
  27
  0
  0
  165
  44
  31
  905
  </orxBandPassAdcProfile>

 </obsRx>

 <lpbk>
  <rxFirDecimation=4>
  <rhb1Decimation=2>
  <outputRate_kHz=61440>
  <rfBandwidth_Hz=25000000>
  <rxBbf3dBCorner_kHz=225000>

  <filter FIR gain_dB=-12 num=72>
  -8
  126
  92
  46
  -78
  -189
  -223
  -92
  149
  387
  425
  185
  -275
  -685
  -757
  -322
  457
  1155
  1262
  549
  -737
  -1878
  -2072
  -922
  1170
  3076
  3455
  1580
  -2049
  -5623
  -6715
  -3424
  4523
  15336
  25683
  31998
  31998
  25683
  15336
  4523
  -3424
  -6715
  -5623
  -2049
  1580
  3455
  3076
  1170
  -922
  -2072
  -1878
  -737
  549
  1262
  1155
  457
  -322
  -757
  -685
  -275
  185
  425
  387
  149
  -92
  -223
  -189
  -78
  46
  92
  126
  -8
  </filter>

  <lpbkAdcProfile num=42>
  265
  146
  181
  90
  1280
  366
  1257
  27
  1258
  17
  718
  39
  48
  46
  27
  161
  0
  0
  0
  0
  40
  0
  7
  6
  42
  0
  7
  6
  42
  0
  25
  27
  0
  0
  25
  27
  0
  0
  165
  44
  31
  905
  </lpbkAdcProfile>
 </lpbk>

 <tx name=Tx 50.00MHz, InputRate 61.44MHz, TotalInterpolation 32>
  <txChannels=TAL_TX1TX2>
  <dacDiv=1>
  <txFirInterpolation=4>
  <thb1Interpolation=2>
  <thb2Interpolation=2>
  <thb3Interpolation=2>
  <txInt5Interpolation=1>
  <txInputRate_kHz=61440>
  <primarySigBandwidth_Hz=25000000>
  <rfBandwidth_Hz=50000000>
  <txDac3dBCorner_kHz=187000>
  <txBbf3dBCorner_kHz=56000>

  <filter FIR gain_dB=6 numFirCoefs=80>
  34
  -20
  -29
  -30
  -46
  54
  82
  70
  52
  -116
  -163
  -124
  -46
  206
  290
  200
  35
  -350
  -475
  -316
  12
  579
  759
  490
  -98
  -915
  -1171
  -722
  282
  1492
  1890
  1127
  -633
  -2675
  -3471
  -2089
  1752
  7282
  12571
  15889
  15889
  12571
  7282
  1752
  -2089
  -3471
  -2675
  -633
  1127
  1890
  1492
  282
  -722
  -1171
  -915
  -98
  490
  759
  579
  12
  -316
  -475
  -350
  35
  200
  290
  206
  -46
  -124
  -163
  -116
  52
  70
  82
  54
  -46
  -30
  -29
  -20
  34
  </filter>
 </tx>
</profile>

              

              


              
			
              

		
		
		
		
	
              
	
              
		
              
			
		
              
	
              
	
              
		
						
						
				
						
				
				
		
		
              
			
		
              
	
              

              

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Reply

              


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													0
							
			
				
									
							        
			
			
			
              •  Analog Employees  
              
            
			                            
                        
                on Mar 27, 2023 10:05 AM
            
            
												
						in reply to Meghraj
					
									
              
	
              

		
		
              
					
              Can you try with the attached profile? 
              

               



              
    
              
        Fullscreen
        Tx_BW50_IR61p44_Rx_BW50_OR61p44_ORx_BW50_OR61p44.txt
        Download
    
              
    
              <profile Talise version=1 name=Tx_BW50_IR61p44_Rx_BW50_OR61p44_ORx_BW50_OR61p44>
 <clocks>
  <deviceClock_kHz=122880>
  <clkPllVcoFreq_kHz=9830400>
  <clkPllHsDiv=2.5>
 </clocks>

 <rx name=Rx 50.00MHz, OutputRate 61.44MHz, TotalDecimation 32>
  <rxChannels=TAL_RX1RX2>
  <rxFirDecimation=4>
  <rxDec5Decimation=4>
  <rhb1Decimation=2>
  <rxOutputRate_kHz=61440>
  <rfBandwidth_Hz=50000000>
  <rxBbf3dBCorner_kHz=50000>
  <rxDdcMode=0>

  <rxNcoShifterCfg>
   <bandAInputBandWidth_kHz=0>
   <bandAInputCenterFreq_kHz=0>
   <bandANco1Freq_kHz=0>
   <bandANco2Freq_kHz=0>
   <bandBInputBandWidth_kHz=0>
   <bandBInputCenterFreq_kHz=0>
   <bandBNco1Freq_kHz=0>
   <bandBNco2Freq_kHz=0>
  </rxNcoShifterCfg>

  <filter FIR gain_dB=-6 numFirCoefs=72>
  -26
  89
  47
  39
  -40
  -104
  -137
  -65
  71
  221
  254
  130
  -140
  -388
  -454
  -216
  232
  659
  751
  365
  -381
  -1069
  -1231
  -604
  603
  1755
  2060
  1060
  -1008
  -3146
  -3975
  -2381
  1838
  7716
  13398
  16883
  16883
  13398
  7716
  1838
  -2381
  -3975
  -3146
  -1008
  1060
  2060
  1755
  603
  -604
  -1231
  -1069
  -381
  365
  751
  659
  232
  -216
  -454
  -388
  -140
  130
  254
  221
  71
  -65
  -137
  -104
  -40
  39
  47
  89
  -26
  </filter>

  <rxAdcProfile num=42>
  265
  146
  181
  90
  1280
  366
  1257
  27
  1258
  17
  718
  39
  48
  46
  27
  161
  0
  0
  0
  0
  40
  0
  7
  6
  42
  0
  7
  6
  42
  0
  25
  27
  0
  0
  25
  27
  0
  0
  165
  44
  31
  905
  </rxAdcProfile>
 </rx>

 <obsRx name=Rx 50.00MHz, OutputRate 61.44MHz, TotalDecimation 32>
  <obsRxChannelsEnable=TAL_ORX1ORX2>
  <enAdcStitching=0>
  <rxFirDecimation=4>
  <rxDec5Decimation=4>
  <rhb1Decimation=2>
  <orxOutputRate_kHz=61440>
  <rfBandwidth_Hz=50000000>
  <rxBbf3dBCorner_kHz=225000>
  <orxDdcMode=0>

  <filter FIR gain_dB=-12 numFirCoefs=72>
  -8
  126
  92
  46
  -78
  -189
  -223
  -92
  149
  387
  425
  185
  -275
  -685
  -757
  -322
  457
  1155
  1262
  549
  -737
  -1878
  -2072
  -922
  1170
  3076
  3455
  1580
  -2049
  -5623
  -6715
  -3424
  4523
  15336
  25683
  31998
  31998
  25683
  15336
  4523
  -3424
  -6715
  -5623
  -2049
  1580
  3455
  3076
  1170
  -922
  -2072
  -1878
  -737
  549
  1262
  1155
  457
  -322
  -757
  -685
  -275
  185
  425
  387
  149
  -92
  -223
  -189
  -78
  46
  92
  126
  -8
  </filter>

  <orxLowPassAdcProfile num=42>
  265
  146
  181
  90
  1280
  366
  1257
  27
  1258
  17
  718
  39
  48
  46
  27
  161
  0
  0
  0
  0
  40
  0
  7
  6
  42
  0
  7
  6
  42
  0
  25
  27
  0
  0
  25
  27
  0
  0
  165
  44
  31
  905
  </orxLowPassAdcProfile>

  <orxBandPassAdcProfile num=42>
  265
  146
  181
  90
  1280
  366
  1257
  27
  1258
  17
  718
  39
  48
  46
  27
  161
  0
  0
  0
  0
  40
  0
  7
  6
  42
  0
  7
  6
  42
  0
  25
  27
  0
  0
  25
  27
  0
  0
  165
  44
  31
  905
  </orxBandPassAdcProfile>

 </obsRx>

 <lpbk>
  <rxFirDecimation=4>
  <rhb1Decimation=2>
  <outputRate_kHz=61440>
  <rfBandwidth_Hz=25000000>
  <rxBbf3dBCorner_kHz=225000>

  <filter FIR gain_dB=-12 num=72>
  -8
  126
  92
  46
  -78
  -189
  -223
  -92
  149
  387
  425
  185
  -275
  -685
  -757
  -322
  457
  1155
  1262
  549
  -737
  -1878
  -2072
  -922
  1170
  3076
  3455
  1580
  -2049
  -5623
  -6715
  -3424
  4523
  15336
  25683
  31998
  31998
  25683
  15336
  4523
  -3424
  -6715
  -5623
  -2049
  1580
  3455
  3076
  1170
  -922
  -2072
  -1878
  -737
  549
  1262
  1155
  457
  -322
  -757
  -685
  -275
  185
  425
  387
  149
  -92
  -223
  -189
  -78
  46
  92
  126
  -8
  </filter>

  <lpbkAdcProfile num=42>
  265
  146
  181
  90
  1280
  366
  1257
  27
  1258
  17
  718
  39
  48
  46
  27
  161
  0
  0
  0
  0
  40
  0
  7
  6
  42
  0
  7
  6
  42
  0
  25
  27
  0
  0
  25
  27
  0
  0
  165
  44
  31
  905
  </lpbkAdcProfile>
 </lpbk>

 <tx name=Tx 50.00MHz, InputRate 61.44MHz, TotalInterpolation 32>
  <txChannels=TAL_TX1TX2>
  <dacDiv=1>
  <txFirInterpolation=4>
  <thb1Interpolation=2>
  <thb2Interpolation=2>
  <thb3Interpolation=2>
  <txInt5Interpolation=1>
  <txInputRate_kHz=61440>
  <primarySigBandwidth_Hz=25000000>
  <rfBandwidth_Hz=50000000>
  <txDac3dBCorner_kHz=187000>
  <txBbf3dBCorner_kHz=56000>

  <filter FIR gain_dB=6 numFirCoefs=80>
  34
  -20
  -29
  -30
  -46
  54
  82
  70
  52
  -116
  -163
  -124
  -46
  206
  290
  200
  35
  -350
  -475
  -316
  12
  579
  759
  490
  -98
  -915
  -1171
  -722
  282
  1492
  1890
  1127
  -633
  -2675
  -3471
  -2089
  1752
  7282
  12571
  15889
  15889
  12571
  7282
  1752
  -2089
  -3471
  -2675
  -633
  1127
  1890
  1492
  282
  -722
  -1171
  -915
  -98
  490
  759
  579
  12
  -316
  -475
  -350
  35
  200
  290
  206
  -46
  -124
  -163
  -116
  52
  70
  82
  54
  -46
  -30
  -29
  -20
  34
  </filter>
 </tx>
</profile>

              

              


              
			
              

		
		
		
		
	
              
	
              
		
              
			
		
              
	
              
	
              
		
						
						
				
						
				
				
		
		
              
			
		
              
	
              

              

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