Jesd204 problem when loading profile with zc706 carrier board

Can you try by loading profiles generated from the Filter wizard tool? You can download it from the below link:

https://wiki.analog.com/resources/eval/user-guides/adrv9009 

Can you share example profile for zc706 with 200 mhz bandwidth?

Refer to the attached profile.ezone.zip

It doesn't work for zc706 carrier board, I think zc706 can not support higher rate with adrv9009 due to limited jesd204 lane rate. Can you verify this assuming by asking to board specialists?

No, the higher rates works fine with ADRV9009+ZC706 board. Can you try configuring using TES GUI?

Download the windows based SD card image from the below link(download the AD9371 image and then update platform files by going to the tool option in GUI and then use the same image for ADRV9009):

https://www.analog.com/en/design-center/landing-pages/001/transceiver-evaluation-software.html 

Download the TES GUUI from the below link:

 "ADRV9009_Transceiver_Evaluation_Software_FULL.exe").  https://www.analog.com/media/en/evaluation-boards-kits/evaluation-software/adrv9009-eval-software-with-gui.zip 

There are more than one version of zc706 with different SOC like XC7Z7045-2FFG900-x where x is equal 1,2 and 3.This represents the speed grade. Clock speed changes corresponding the speed grade. My SOC is XC7Z7045-2FFG900C but this product has been frozen with release of vivado 2015.4.I think my zc706 board CPLL can not support higher lane rate due to discontinuenity. After switching CPPL to QPLL on device tree(XCVR_CPLL->XCVR_QPLL) and small modification on vivado(disable tx_xcvr qpll enable, enable rx_xcvr qpll enable,set 11 rx_xcvr sys clk sel for qpll and changing qpll reference) it works. If anyone faces this problem i hope it will help. You deserve ekiz yatak.

Hi,

We are using ADRV9009 + TPG-ZYNQ3, for our application we need to evaluate if the transceiver is capable of reaching 200 MHz bandwidth (245.76 MHz sampling rate) on RX and TX.

While using TES software to program the device with 200 MHz profile it succeeds, however for our application we are using a third part application that needs the IIO library to work. For this purpose we're using Linux Kuiper last release, and as many have reported, the 200 MHz profile (on RX) can't be loaded, neither the default one nor the others provided in the forums.

As far as I know from reading the documentation and forums, the only probable solution not yet tried is the one proposed by saldirayabi66  invlolving devicetree and HDL modifications

Please could you or anyone give some details about how to make these modifications as I have limited experience in FPGA IP design, for instance:

* Regarding Devicetree file, is it sufficient to convert .dtb to .dts, edit and then recompile?

* If possible, could you, please explain a bit more in depth the procedure to do in Vivado? which files and what to do after the modifications? I've been through some of many HDL documents available but couldn't make my way.

Much gratitude for any help,

Jam

Please do not post under answered questions . If you still face issue , post a new query with full details  so that we can look into it.

Çıkar şu üstündekileri ne dediğin anlaşılmıyor!

Please do not post for answered questions, if you have any questions please post a new query with all the details.

Please do not post for answered questions, if you have any questions please post a new query with all the details.