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Will adrv9009 adc overload?

Category: Hardware
Product Number: adrv9009

Hi,I am using the hdl 'master' branch . And i am using no-os master branch. And I am using the project design for  zc706 and EVAL-ADRV9008/9.

The signal power input to rx1 channel is -9 dBm to -4dBm.The agc index is around 0xfb ~0xe3.

I'm using agc peak mode. I found that sometimes the adc signal has error values while the agc changing.

How can I fix this? Thanks.

Parents
  • In my case ,the framer A status is 0x27.Will this cause the adc error?

  • You can readback the RX dec power(API GetRxDecPower)

    Is it the API below ?

    uint32_t TALISE_getRxDecPower(taliseDevice_t *device,
    			      taliseRxChannels_t rxChannel, uint16_t *rxDecPower_mdBFS);

    share with us  the AGC settings and the threshold values that you are using.

    I have already changed the agc settings now. I attach it below. The saturation still exist when the input signal greater than -11 dBm . I know that adrv9009 can not  use beyond that input level , but there is a possibility that the input signal greater than -11dbm.

    Is there anything wrong with the agc settings ?

    taliseAgcCfg_t rxAgcCtrl = {
    	2,
    	255,
    	195,
    	255,
    	195,
    	15360,  /* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 122.88 Mhz) */
    	0,
    	0,
    	16,
    	0,
    	1,     //agcChangeGainIfThreshHigh. 
    	1,     //agcPeakThreshGainControlMode.
    	0,
    	0,
    	1,
    	31,
    	246,
    	4,
    	1,          /*agcEnableFastRecoveryLoop!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */
    	/* agcPower */
    	{
    		0,      /*powerEnableMeasurement!<1-bit field, enables the Rx power measurement block. */
    		1,      /*powerUseRfirOut!<1-bit field, allows using Rx PFIR for power measurement. */
    		0,      /*powerUseBBDC2!<1-bit field, allows to use the output of the second digital offset block in the Rx datapath for power measurement. */
    		14,      /*underRangeHighPowerThresh!<AGC power measurement detect lower 0 threshold. Default = -12dBFS == 5, 7-bit register value where max = 0x7F, min = 0x00 */
    		2,      /*underRangeLowPowerThresh!<AGC power measurement detect lower 1 threshold. Default = (offset) 4dB == 0, 4-bit register value where  max = 0xF, min = 0x00 */
    		2,      /*underRangeHighPowerGainStepRecovery!<AGC power measurement detect lower 0 recovery gain step. Default = 2dB - based on gain table step  size, 5-bit register value where max = 0x1F, min = 0x00 */
    		4,      /*underRangeLowPowerGainStepRecovery!<AGC power measurement detect lower 1 recovery gain step. Default = 4dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
    		5,      /*!< power measurement duration used by the decimated power block. Default = 0x05, 5-bit register value where max = 0x1F, min = 0x00 */
    		5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
    		1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
    		5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
    		1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
    		10,      /*upper0PowerThresh!<Default value should be 2*/
    		2,      /*upper1PowerThresh*/
    		1       /*powerLogShift*/
    	},
    	/* agcPeak */
    	{
    		4000,        /*!<1st update interval for the multiple time constant in AGC loop mode, Default:205. */
    		2,          /*agcUnderRangeMidInterval!<sets the 2nd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of  agcUnderRangeLowInterval聽聽, Default: 4 */
    		4,          /*agcUnderRangeHighInterval!<sets the 3rd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeMidInterval and agcUnderRangeLowInterval, Default: 4 */
    		41,         /*apdHighThresh!<AGC APD high threshold. Default=0x1F, 6-bit register value where max=0x3F, min =0x00 */
    		49,         /* Not applicable!< AGC APD high threshold in low gain mode. Valid range is 7 to 49. Recommended to be 3dB above apdHighThresh */
    		26,          /*apdLowThresh!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max =0x3F, min = 0x00 */
    		19,         /* Not applicable!< AGC APD low threshold in low gain mode. Valid range is 7 to 49. Recommended to be 3dB above apdLowThresh */
    		6,          /*apdUpperThreshPeakExceededCnt!<AGC APD peak detect upper threshold count. Default = 0x06 8-bit register value where max = 0xFF, min = 0x20  */
    		3,          /*apdLowerThreshPeakExceededCnt!<AGC APD peak detect lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00聽 */
    		4,          /*apdGainStepAttack!<AGC APD peak detect attack gain step. Default = 2dB step - based on gain table step size, 5-bit register  value, where max = 0x1F, min = 0x00  */
    		2,          /*apdGainStepRecovery!<AGC APD gain index step size. Recommended to be same as hb2GainStepRecovery. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00  */
    		1,          /*enableHb2Overload!<1-bit field, enables or disables the HB2 overload detector.  */
    		1,          /*hb2OverloadDurationCnt!<3-bit field. Sets the window of clock cycles (at the HB2 output rate) to meet the overload count. */
    		1,          /*hb2OverloadThreshCnt!<4-bit field. Sets the number of actual overloads required to trigger the overload signal.  */
    		203,        /*hb2HighThresh!<AGC decimator output high threshold. Default = 0xB5, 8-bit register value where max = 0xFF, min = 0x00 */
    		80,         /*hb2UnderRangeLowThresh!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
    		100,         /*hb2UnderRangeMidThresh!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
    		128,        /*hb2UnderRangeHighThresh!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
    		6,          /*hb2UpperThreshPeakExceededCnt!<AGC HB2 output upper threshold count. Default = 0x06, 8-bit register value where max = 0xFF, min =  0x20 */
    		3,          /*hb2LowerThreshPeakExceededCnt!<AGC HB2 output lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
    		2,          /*hb2GainStepHighRecovery!<AGC decimator gain index step size. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
    		8,          /*hb2GainStepLowRecovery!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 0 triggers a programmable number  of times. Default = 0x08, 5-bit register value where max = 0x1F, min = 0x00 */
    		4,          /*hb2GainStepMidRecovery!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 1 triggers a programmable number of times. Default = 0x04, 5-bit register value where max = 0x1F, min = 0x00 */
    		4,          /*hb2GainStepAttack!<AGC decimator output attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
    		0,
    		0,
    		3           
    	}
    };

    Are you operating in AGC peak mode or power mode? 

    If you want the AGC to work below -11dBm, try changing the low power thresholds(HB2 underange  threshold and APD low power threshold)

    I am using fast attack, fast recovery, peak detect . If there isn't saturation greater that -11 dBm is fine by me.

  • Is it the API below ?

    Yes. 

    Try using the default AGC settings, and with that, you will not see saturation with input power levels higher than -11dBm, as the AGC will compensate for that by decreasing the gain index.

    APD high threshold and HB2 high threshold should not be the same. Try thresholds as below:

  • Try using the default AGC setting

    Do you mean the default agc setting of TES generate profile talise_config.c? I found saturation first at that agc setting that is why I post question here. And I change the agc setting follow the iron python script from ug1295. as you was saying the agc setting isn't so right?

  • APD high threshold and HB2 high threshold should not be the same.

    Thanks for your reply. I found ug1295 page 132 sadi that :

    I think that means APD high threshold and HB2 high threshold should have an equivalent dBFS value. Am I wrong?

  • I think that means APD high threshold and HB2 high threshold should have an equivalent dBFS value. Am I wrong?

    They can be equivalent, but are not exactly equal. 

    The threshold values that you are using are correct, but the dBFs values are not correct. There will be difference in decimals between them.

      

    Can you try with the attached config files and check in your eval board? You will not see saturation above -11dBm power.

    Ezone_config_files.zip

  • I have tried the TES default profile agc setting. It has saturation when the signal power suddenly rise.

    //From TES default profile.
    taliseAgcCfg_t rxAgcCtrl = {
        4,
        255,
        195,
        255,
        195,
        15360,  /* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 245.76 Mhz) */
        10,
        10,
        16,
        0,
        1,
        0,
        0,
        0,
        1,
        31,
        246,
        4,
        1,          /*!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */
        /* agcPower */
        {
            1,      /*!<1-bit field, enables the Rx power measurement block. */
            1,      /*!<1-bit field, allows using Rx PFIR for power measurement. */
            0,      /*!<1-bit field, allows to use the output of the second digital offset block in the Rx datapath for power measurement. */
            9,      /*!<AGC power measurement detect lower 0 threshold. Default = -12dBFS == 5, 7-bit register value where max = 0x7F, min = 0x00 */
            2,      /*!<AGC power measurement detect lower 1 threshold. Default = (offset) 4dB == 0, 4-bit register value where  max = 0xF, min = 0x00 */
            4,      /*!<AGC power measurement detect lower 0 recovery gain step. Default = 2dB - based on gain table step  size, 5-bit register value where max = 0x1F, min = 0x00 */
            4,      /*!<AGC power measurement detect lower 1 recovery gain step. Default = 4dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
            5,      /*!< power measurement duration used by the decimated power block. Default = 0x05, 5-bit register value where max = 0x1F, min = 0x00 */
            5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
            1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
            5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
            1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
            2,      /*!<Default value should be 2*/
            0,
            0
        },
        /* agcPeak */
        {
            205,        /*!<1st update interval for the multiple time constant in AGC loop mode, Default:205. */
            2,          /*!<sets the 2nd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of  agcUnderRangeLowInterval  , Default: 4 */
            4,          /*!<sets the 3rd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeMidInterval and agcUnderRangeLowInterval, Default: 4 */
            39,         /*!<AGC APD high threshold. Default=0x1F, 6-bit register value where max=0x3F, min =0x00 */
            49,         /*!<AGC APD peak detect high threshold. default = 0x1F, 6-bit register value where max = 0x3F, min = 0x00.  Set to 3dB below apdHighThresh */
            23,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max =0x3F, min = 0x00 */
            19,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max = 0x3F, min = 0x00 . Set to 3dB below apdLowThresh  */
            6,          /*!<AGC APD peak detect upper threshold count. Default = 0x06 8-bit register value where max = 0xFF, min = 0x20  */
            3,          /*!<AGC APD peak detect lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00  */
            4,          /*!<AGC APD peak detect attack gain step. Default = 2dB step - based on gain table step size, 5-bit register  value, where max = 0x1F, min = 0x00  */
            2,          /*!<AGC APD gain index step size. Recommended to be same as hb2GainStepRecovery. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00  */
            1,          /*!<1-bit field, enables or disables the HB2 overload detector.  */
            1,          /*!<3-bit field. Sets the window of clock cycles (at the HB2 output rate) to meet the overload count. */
            1,          /*!<4-bit field. Sets the number of actual overloads required to trigger the overload signal.  */
            181,        /*!<AGC decimator output high threshold. Default = 0xB5, 8-bit register value where max = 0xFF, min = 0x00 */
            45,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
            90,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
            128,        /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
            6,          /*!<AGC HB2 output upper threshold count. Default = 0x06, 8-bit register value where max = 0xFF, min =  0x20 */
            3,          /*!<AGC HB2 output lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
            2,          /*!<AGC decimator gain index step size. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
            4,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 0 triggers a programmable number  of times. Default = 0x08, 5-bit register value where max = 0x1F, min = 0x00 */
            8,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 1 triggers a programmable number of times. Default = 0x04, 5-bit register value where max = 0x1F, min = 0x00 */
            4,          /*!<AGC decimator output attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
            1,
            0,
            3
        }
    };

    I took a screenshot of the results :

    I will try the new profile. Thanks.

  • The profile you attached is the TES default profile. I have test it before. It can not overcome the saturation when the signal power rise suddenly.

  • The waveform at the output doesn't look like a CW waveform. Can you perform your tests with CW waveform?

    Also, please try with the profiles that I had shared before

  • It is a tone signal and it's power level switch  between -6dBm and -36dBm in dozens of ms . I think it is a CW waveform?

  • It is a tone signal and it's power level switch  between -6dBm and -36dBm in dozens of ms .

    Can you share the FFT plot of the output that you are seeing? 

    What is your power level hop time? AGC takes some time(depends on the FIR rate or the input sampling rates and clock rates) to adjust the RX gain to its final value. So, if the stay time in a particular power level is very less, then you can see the fluctuations. 

    Stay at -6dBm input power level for some time with AGC peak mode enabled, and share with us the time domain as well as the frequency domain plot of the output

Reply
  • It is a tone signal and it's power level switch  between -6dBm and -36dBm in dozens of ms .

    Can you share the FFT plot of the output that you are seeing? 

    What is your power level hop time? AGC takes some time(depends on the FIR rate or the input sampling rates and clock rates) to adjust the RX gain to its final value. So, if the stay time in a particular power level is very less, then you can see the fluctuations. 

    Stay at -6dBm input power level for some time with AGC peak mode enabled, and share with us the time domain as well as the frequency domain plot of the output

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