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Will adrv9009 adc overload?

Category: Hardware
Product Number: adrv9009

Hi,I am using the hdl 'master' branch . And i am using no-os master branch. And I am using the project design for  zc706 and EVAL-ADRV9008/9.

The signal power input to rx1 channel is -9 dBm to -4dBm.The agc index is around 0xfb ~0xe3.

I'm using agc peak mode. I found that sometimes the adc signal has error values while the agc changing.

How can I fix this? Thanks.

Parents
  • In my case ,the framer A status is 0x27.Will this cause the adc error?

  • If its a modulated signal , you have to consider PAR. If you consider PAR of 10dB then you can feed -21dBm into the RX1 port .

    You mean that the -11dBm is input signal peak useable level?

    Are you operating the chip in TDD mode only while giving TDD signal as an input ? Ensure that TDD signal timing should match with the TX ON/OFF periods of our chip.

    I test the cw dds signal , while the adc value approximate 32768 the adc will get errors like below picture.

    1. How to set the adrv9009 adc keep at 32768 if the adc value great than 32768? I mean can the adc clipping?

    2. The agc still can not adjust until signal great than -9dBm , even I change the apdHighThresh to  10,apdLowThresh to 7.I think the apdHighThresh will affect the gain attack , but change it only affect the adc peak value as I see.Is there anything I misunderstand to the apdHighThresh?

    I'm using agc peak detect mode,and I test the peak/power mode too. It is the same. I think below is the right API to use,and the other thing needs to do is set the parameter in the taliseAgcCfg_t.

    	agc_status = TALISE_setRxGainControlMode(&tal[0],TAL_AGCSLOW);
    	if (agc_status)
    		printf("TALISE_setRxGainControlMode() failed with status %d\n", agc_status);

  • Yes , the peak power will be -11dBm . 

    Are you operating the chip in TDD mode ? If so what is the TDD timing ? 

  • Are you operating the chip in TDD mode ? If so what is the TDD timing ? 

    All the result in this post is using continue wave.I want to use tdd mode,I am using tx_enable on and off the tx channel. The tdd timing is transmit 4 ms then wait for 16 ms and then transmit 4ms , it is a cycle.What is your point?

  • 1. How to set the adrv9009 adc keep at 32768 if the adc value great than 32768? I mean can the adc clipping?

    I found the answer  in this post : ADRV9008-1 / ADRV9009 Rx Clipping Behaviour. From the post adrv9009 can't clipping like typical ADC, unbelieveable.

  • Check whether the TDD Tx burst period and the TX ON period in the chip is matching while you are operating in TDD mode .

  • For so called "TDD mode" I just use adrv9009_tx1_enable to control the tx channel on and off,the switch time of adrv9009_tx1_enable is matching with the signal burst period. Is there any other period do I need to care ?

    Is there a TDD mode that I need to set the adrv9009 ?

  • As i have mentioned  we need to provide an RF input signal level that's within the dynamic range, the max. input level is -11dBm CW or -21dBm modulated signal with PAR of 10dB(As an example)

    The ADC errors that you are getting are observed when you are operating at -9dBm to -4dBm with modulated signal at which level ,the performance is not guaranteed.

    Do you see these ADC errors when you operate at low powers as well? If so, can you please share us your complete AGC configuration parameters?

  • Do you see these ADC errors when you operate at low powers as well?

    seems not.

    The ADC errors that you are getting are observed when you are operating at -9dBm to -4dBm with modulated signal at which level ,the performance is not guaranteed.

    when I operating under -11dBm the agc always at top index 255. Isn't this a problem ?how to fix it?

  • The full scale value of ADC is 7dBm and with input signal level of -11dBm at gain index of 255, the ADC sees 7dBm hence the gain index staying at 255 is fine as the ADC is not saturating.

    It looks like the AGC is not acting as you are seeing the ADC errors above -11dBm signal level. Can you change the APD high threshold to 38 and low threshold to 25 and check for the ADC errors?

  • The full scale value of ADC is 7dBm and with input signal level of -11dBm at gain index of 255, the ADC sees 7dBm hence the gain index staying at 255 is fine as the ADC is not saturating.

    Do you mean that the scale of ADC is -11dBm ~ 7dBm , so the gain 255 correspond to -11dBm and gain 195 correspond to 7dBm? I am confused. Because I think the peak power of input signal level is -11 dBm ,so the gain 195 should correspond to -11dBm.

    Can you change the APD high threshold to 38 and low threshold to 25 and check for the ADC errors?

    Will try.

Reply
  • The full scale value of ADC is 7dBm and with input signal level of -11dBm at gain index of 255, the ADC sees 7dBm hence the gain index staying at 255 is fine as the ADC is not saturating.

    Do you mean that the scale of ADC is -11dBm ~ 7dBm , so the gain 255 correspond to -11dBm and gain 195 correspond to 7dBm? I am confused. Because I think the peak power of input signal level is -11 dBm ,so the gain 195 should correspond to -11dBm.

    Can you change the APD high threshold to 38 and low threshold to 25 and check for the ADC errors?

    Will try.

Children
  • Do you mean that the scale of ADC is -11dBm ~ 7dBm , so the gain 255 correspond to -11dBm and gain 195 correspond to 7dBm? I am confused. Because I think the peak power of input signal level is -11 dBm ,so the gain 195 should correspond to -11dBm.

    No, with an RF input signal level of -11dBm (at the RX port of the chip)  with gain index of 255, the  gain is 18dB which means the signal level at ADC input is 7dBm which is its full scale value. Please note that -11dBm is the max. input signal level. (Be it CW or the Peak signal level of a modulated signal)

  • Thanks for your reply. We use ad9361 before and ad9361 will saturate rather than  wrapping ,Can I ask why the adrv9009 can not saturate ?

  • We are working on this, will get back 

  • Is this something that no-os can handle?

  • I test the cw dds signal , while the adc value approximate 32768 the adc will get errors like below picture.

    A time domain signal like this indicates a saturation at the RX path. You can readback the RX dec power(API GetRxDecPower) and you will see a value of zero at the output.

    Since you are doing the tests in AGC mode, you should not see saturation at the output.

    When you vary the signal from -9dBm to -4dBm(the power range in which you are seeing the issue), can you readback the gain index using API GetRxGain? Also, share with us  the AGC settings and the threshold values that you are using.

    when I operating under -11dBm the agc always at top index 255. Isn't this a problem ?how to fix it?

    You need to change the thresholds for that. Are you operating in AGC peak mode or power mode? 

    If you want the AGC to work below -11dBm, try changing the low power thresholds(HB2 underange  threshold and APD low power threshold)

  • You can readback the RX dec power(API GetRxDecPower)

    Is it the API below ?

    uint32_t TALISE_getRxDecPower(taliseDevice_t *device,
    			      taliseRxChannels_t rxChannel, uint16_t *rxDecPower_mdBFS);

    share with us  the AGC settings and the threshold values that you are using.

    I have already changed the agc settings now. I attach it below. The saturation still exist when the input signal greater than -11 dBm . I know that adrv9009 can not  use beyond that input level , but there is a possibility that the input signal greater than -11dbm.

    Is there anything wrong with the agc settings ?

    taliseAgcCfg_t rxAgcCtrl = {
    	2,
    	255,
    	195,
    	255,
    	195,
    	15360,  /* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 122.88 Mhz) */
    	0,
    	0,
    	16,
    	0,
    	1,     //agcChangeGainIfThreshHigh. 
    	1,     //agcPeakThreshGainControlMode.
    	0,
    	0,
    	1,
    	31,
    	246,
    	4,
    	1,          /*agcEnableFastRecoveryLoop!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */
    	/* agcPower */
    	{
    		0,      /*powerEnableMeasurement!<1-bit field, enables the Rx power measurement block. */
    		1,      /*powerUseRfirOut!<1-bit field, allows using Rx PFIR for power measurement. */
    		0,      /*powerUseBBDC2!<1-bit field, allows to use the output of the second digital offset block in the Rx datapath for power measurement. */
    		14,      /*underRangeHighPowerThresh!<AGC power measurement detect lower 0 threshold. Default = -12dBFS == 5, 7-bit register value where max = 0x7F, min = 0x00 */
    		2,      /*underRangeLowPowerThresh!<AGC power measurement detect lower 1 threshold. Default = (offset) 4dB == 0, 4-bit register value where  max = 0xF, min = 0x00 */
    		2,      /*underRangeHighPowerGainStepRecovery!<AGC power measurement detect lower 0 recovery gain step. Default = 2dB - based on gain table step  size, 5-bit register value where max = 0x1F, min = 0x00 */
    		4,      /*underRangeLowPowerGainStepRecovery!<AGC power measurement detect lower 1 recovery gain step. Default = 4dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
    		5,      /*!< power measurement duration used by the decimated power block. Default = 0x05, 5-bit register value where max = 0x1F, min = 0x00 */
    		5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
    		1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
    		5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
    		1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
    		10,      /*upper0PowerThresh!<Default value should be 2*/
    		2,      /*upper1PowerThresh*/
    		1       /*powerLogShift*/
    	},
    	/* agcPeak */
    	{
    		4000,        /*!<1st update interval for the multiple time constant in AGC loop mode, Default:205. */
    		2,          /*agcUnderRangeMidInterval!<sets the 2nd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of  agcUnderRangeLowInterval聽聽, Default: 4 */
    		4,          /*agcUnderRangeHighInterval!<sets the 3rd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeMidInterval and agcUnderRangeLowInterval, Default: 4 */
    		41,         /*apdHighThresh!<AGC APD high threshold. Default=0x1F, 6-bit register value where max=0x3F, min =0x00 */
    		49,         /* Not applicable!< AGC APD high threshold in low gain mode. Valid range is 7 to 49. Recommended to be 3dB above apdHighThresh */
    		26,          /*apdLowThresh!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max =0x3F, min = 0x00 */
    		19,         /* Not applicable!< AGC APD low threshold in low gain mode. Valid range is 7 to 49. Recommended to be 3dB above apdLowThresh */
    		6,          /*apdUpperThreshPeakExceededCnt!<AGC APD peak detect upper threshold count. Default = 0x06 8-bit register value where max = 0xFF, min = 0x20  */
    		3,          /*apdLowerThreshPeakExceededCnt!<AGC APD peak detect lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00聽 */
    		4,          /*apdGainStepAttack!<AGC APD peak detect attack gain step. Default = 2dB step - based on gain table step size, 5-bit register  value, where max = 0x1F, min = 0x00  */
    		2,          /*apdGainStepRecovery!<AGC APD gain index step size. Recommended to be same as hb2GainStepRecovery. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00  */
    		1,          /*enableHb2Overload!<1-bit field, enables or disables the HB2 overload detector.  */
    		1,          /*hb2OverloadDurationCnt!<3-bit field. Sets the window of clock cycles (at the HB2 output rate) to meet the overload count. */
    		1,          /*hb2OverloadThreshCnt!<4-bit field. Sets the number of actual overloads required to trigger the overload signal.  */
    		203,        /*hb2HighThresh!<AGC decimator output high threshold. Default = 0xB5, 8-bit register value where max = 0xFF, min = 0x00 */
    		80,         /*hb2UnderRangeLowThresh!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
    		100,         /*hb2UnderRangeMidThresh!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
    		128,        /*hb2UnderRangeHighThresh!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
    		6,          /*hb2UpperThreshPeakExceededCnt!<AGC HB2 output upper threshold count. Default = 0x06, 8-bit register value where max = 0xFF, min =  0x20 */
    		3,          /*hb2LowerThreshPeakExceededCnt!<AGC HB2 output lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
    		2,          /*hb2GainStepHighRecovery!<AGC decimator gain index step size. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
    		8,          /*hb2GainStepLowRecovery!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 0 triggers a programmable number  of times. Default = 0x08, 5-bit register value where max = 0x1F, min = 0x00 */
    		4,          /*hb2GainStepMidRecovery!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 1 triggers a programmable number of times. Default = 0x04, 5-bit register value where max = 0x1F, min = 0x00 */
    		4,          /*hb2GainStepAttack!<AGC decimator output attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
    		0,
    		0,
    		3           
    	}
    };

    Are you operating in AGC peak mode or power mode? 

    If you want the AGC to work below -11dBm, try changing the low power thresholds(HB2 underange  threshold and APD low power threshold)

    I am using fast attack, fast recovery, peak detect . If there isn't saturation greater that -11 dBm is fine by me.

  • Is it the API below ?

    Yes. 

    Try using the default AGC settings, and with that, you will not see saturation with input power levels higher than -11dBm, as the AGC will compensate for that by decreasing the gain index.

    APD high threshold and HB2 high threshold should not be the same. Try thresholds as below:

  • Try using the default AGC setting

    Do you mean the default agc setting of TES generate profile talise_config.c? I found saturation first at that agc setting that is why I post question here. And I change the agc setting follow the iron python script from ug1295. as you was saying the agc setting isn't so right?

  • APD high threshold and HB2 high threshold should not be the same.

    Thanks for your reply. I found ug1295 page 132 sadi that :

    I think that means APD high threshold and HB2 high threshold should have an equivalent dBFS value. Am I wrong?

  • I think that means APD high threshold and HB2 high threshold should have an equivalent dBFS value. Am I wrong?

    They can be equivalent, but are not exactly equal. 

    The threshold values that you are using are correct, but the dBFs values are not correct. There will be difference in decimals between them.

      

    Can you try with the attached config files and check in your eval board? You will not see saturation above -11dBm power.

    Ezone_config_files.zip