Will adrv9009 adc overload?

Can anyone help?Thanks.

In my case ,the framer A status is 0x27.Will this cause the adc error?

1000floors said:

In my case ,the framer A status is 0x27.Will this cause the adc error?

No , It doesn't cause the ADC error .

1000floors said:

The signal power input to rx1 channel is -9 dBm to -4dBm.The agc index is around 0xfb ~0xe3.

-9dBm is CW tone or modulated? We can't go more than -11dBm if its a CW tone . -11dBm is maximum useable input level, see the snippet below from the datasheet

Hi,vanitha .Thanks for your reply.

vanitha said:

-9dBm is CW tone or modulated?

-9dBm is modulated tdd signal.Will this be a problem?

vanitha said:

We can't go more than -11dBm if its a CW tone .

so modulated signal can go into rx1 more than -11dBm?

vanitha said:

maximum useable input level

We found that if the input tdd signal lower than the -11dBm the agc can not reduce the gain and keep stay at index 255, is this normal?

1000floors said:

-9dBm is modulated tdd signal.Will this be a problem?

Yes We will have  a problem even if its TDD .

1000floors said:

so modulated signal can go into rx1 more than -11dBm?

If its a modulated signal , you have to consider PAR. If you consider PAR of 10dB then you can feed -21dBm into the RX1 port .

1000floors said:

We found that if the input tdd signal lower than the -11dBm the agc can not reduce the gain and keep stay at index 255, is this normal?

Are you operating the chip in TDD mode only while giving TDD signal as an input ? Ensure that TDD signal timing should match with the TX ON/OFF periods of our chip.

vanitha said:

If its a modulated signal , you have to consider PAR. If you consider PAR of 10dB then you can feed -21dBm into the RX1 port .

You mean that the -11dBm is input signal peak useable level?

vanitha said:

Are you operating the chip in TDD mode only while giving TDD signal as an input ? Ensure that TDD signal timing should match with the TX ON/OFF periods of our chip.

I test the cw dds signal , while the adc value approximate 32768 the adc will get errors like below picture.

1. How to set the adrv9009 adc keep at 32768 if the adc value great than 32768? I mean can the adc clipping?

2. The agc still can not adjust until signal great than -9dBm , even I change the apdHighThresh to  10,apdLowThresh to 7.I think the apdHighThresh will affect the gain attack , but change it only affect the adc peak value as I see.Is there anything I misunderstand to the apdHighThresh?

I'm using agc peak detect mode,and I test the peak/power mode too. It is the same. I think below is the right API to use,and the other thing needs to do is set the parameter in the taliseAgcCfg_t.

	agc_status = TALISE_setRxGainControlMode(&tal[0],TAL_AGCSLOW);
	if (agc_status)
		printf("TALISE_setRxGainControlMode() failed with status %d\n", agc_status);

Yes , the peak power will be -11dBm . 

Are you operating the chip in TDD mode ? If so what is the TDD timing ? 

vanitha said:

Are you operating the chip in TDD mode ? If so what is the TDD timing ? 

All the result in this post is using continue wave.I want to use tdd mode,I am using tx_enable on and off the tx channel. The tdd timing is transmit 4 ms then wait for 16 ms and then transmit 4ms , it is a cycle.What is your point?

1000floors said:

1. How to set the adrv9009 adc keep at 32768 if the adc value great than 32768? I mean can the adc clipping?

I found the answer  in this post : ADRV9008-1 / ADRV9009 Rx Clipping Behaviour. From the post adrv9009 can't clipping like typical ADC, unbelieveable.

Check whether the TDD Tx burst period and the TX ON period in the chip is matching while you are operating in TDD mode .

Check whether the TDD Tx burst period and the TX ON period in the chip is matching while you are operating in TDD mode .

For so called "TDD mode" I just use adrv9009_tx1_enable to control the tx channel on and off,the switch time of adrv9009_tx1_enable is matching with the signal burst period. Is there any other period do I need to care ?

Is there a TDD mode that I need to set the adrv9009 ?

As i have mentioned  we need to provide an RF input signal level that's within the dynamic range, the max. input level is -11dBm CW or -21dBm modulated signal with PAR of 10dB(As an example)

The ADC errors that you are getting are observed when you are operating at -9dBm to -4dBm with modulated signal at which level ,the performance is not guaranteed.

Do you see these ADC errors when you operate at low powers as well? If so, can you please share us your complete AGC configuration parameters?

vanitha said:

Do you see these ADC errors when you operate at low powers as well?

seems not.

vanitha said:

The ADC errors that you are getting are observed when you are operating at -9dBm to -4dBm with modulated signal at which level ,the performance is not guaranteed.

when I operating under -11dBm the agc always at top index 255. Isn't this a problem ?how to fix it?

The full scale value of ADC is 7dBm and with input signal level of -11dBm at gain index of 255, the ADC sees 7dBm hence the gain index staying at 255 is fine as the ADC is not saturating.

It looks like the AGC is not acting as you are seeing the ADC errors above -11dBm signal level. Can you change the APD high threshold to 38 and low threshold to 25 and check for the ADC errors?

vanitha said:

The full scale value of ADC is 7dBm and with input signal level of -11dBm at gain index of 255, the ADC sees 7dBm hence the gain index staying at 255 is fine as the ADC is not saturating.

Do you mean that the scale of ADC is -11dBm ~ 7dBm , so the gain 255 correspond to -11dBm and gain 195 correspond to 7dBm? I am confused. Because I think the peak power of input signal level is -11 dBm ,so the gain 195 should correspond to -11dBm.

vanitha said:

Can you change the APD high threshold to 38 and low threshold to 25 and check for the ADC errors?

Will try.

1000floors said:

Do you mean that the scale of ADC is -11dBm ~ 7dBm , so the gain 255 correspond to -11dBm and gain 195 correspond to 7dBm? I am confused. Because I think the peak power of input signal level is -11 dBm ,so the gain 195 should correspond to -11dBm.

No, with an RF input signal level of -11dBm (at the RX port of the chip)  with gain index of 255, the  gain is 18dB which means the signal level at ADC input is 7dBm which is its full scale value. Please note that -11dBm is the max. input signal level. (Be it CW or the Peak signal level of a modulated signal)

Thanks for your reply. We use ad9361 before and ad9361 will saturate rather than  wrapping ,Can I ask why the adrv9009 can not saturate ?

We are working on this, will get back 

Is this something that no-os can handle?

1000floors said:

I test the cw dds signal , while the adc value approximate 32768 the adc will get errors like below picture.

A time domain signal like this indicates a saturation at the RX path. You can readback the RX dec power(API GetRxDecPower) and you will see a value of zero at the output.

Since you are doing the tests in AGC mode, you should not see saturation at the output.

When you vary the signal from -9dBm to -4dBm(the power range in which you are seeing the issue), can you readback the gain index using API GetRxGain? Also, share with us  the AGC settings and the threshold values that you are using.

1000floors said:

when I operating under -11dBm the agc always at top index 255. Isn't this a problem ?how to fix it?

You need to change the thresholds for that. Are you operating in AGC peak mode or power mode? 

If you want the AGC to work below -11dBm, try changing the low power thresholds(HB2 underange  threshold and APD low power threshold)