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ADRV9009 multichip sync lost after frequency hopping

Hi,

  I'm using a custom board with 3 adrv9009, and I need use their synchronization features.

  Last year, I asked a question :ADRV9009 MCS and RF PLL Phase Sync Question 

  I adopted the srimoyi's suggestions, it worked well and I used it for a while.

  Now I add the frequency hopping function, the 3 adrv9009 FHM configure as GPIO mode , enbleMCS and I can triger 3 chips simultaneously.

  I wrote a test program to make the LO frequencies of the three chips cyclically hop between 600MHz and 800MHz at intervals of 1000ms. I use a signal source and power splitter to input a 601MHz signal to the 6 rx channels. Most of the time, when the LO frequency hop to 600MHz, the ILA data I collected is shown below, It is synced.

  But sometimes , when the LO frequency hop to 600MHz , some chip is not synced , the ILA data I collected is shown below:

  Look CH5 and CH6, they are on same chip and not sync with other channels. But next time,Freq hop back to 600MHz, they are synchronized again. The probability of the problem is about 1/15,,but not fixed.

  Could anyone give me suggustions to solve the problem?

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Edit time
[edited by: l312361206 at 12:24 AM (GMT 0) on 17 Jun 2020]
Parents
  • Are you hoping the frequency directly from 600MHz to 800MHz and vice versa? hope you are running init calls every time you are hoping(since the change is more than 100MHz). Are you running the full init sequence along with both RFPLL and BBPLL  MCS tracking enabled when you are hoping frequencies?

    • Are you hoping the frequency directly from 600MHz to 800MHz and vice versa? hope you are running init calls every time you are hoping(since the change is more than 100MHz).

    Yes,I hoping the frequency directly from 600MHz to 800MHz and then from 800MHz to 600MHz . But I did not run init calls do other operation , like exit fhm or re-run

    • Are you running the full init sequence along with both RFPLL and BBPLL  MCS tracking enabled when you are hoping frequencies?

    NO, after hopping, I did't do other operations, not re-run init sequence an not exit fhm. I thougth the member enableMcsSync in taliseFhmMode_t struct  set to 1 will be worked for hopping . And the most important reason is that I need more than 1000 hops per second, if I re-run the full init sequence, It must be out of my requirement.

    I also found if I just exit the async chip's FHM mode (full exit), its tow channels will be synced again. I viewed the topic:FHM Calibration Resolution, I think exiting FHM will cause the calibration and tracking functions to re-run, that cause their phase re-sync again. But from exit  to enter fhm and vice versa will consume a lot of time, especially the commands of the three chips need to be transmitted in sequence by SPI.

Reply
    • Are you hoping the frequency directly from 600MHz to 800MHz and vice versa? hope you are running init calls every time you are hoping(since the change is more than 100MHz).

    Yes,I hoping the frequency directly from 600MHz to 800MHz and then from 800MHz to 600MHz . But I did not run init calls do other operation , like exit fhm or re-run

    • Are you running the full init sequence along with both RFPLL and BBPLL  MCS tracking enabled when you are hoping frequencies?

    NO, after hopping, I did't do other operations, not re-run init sequence an not exit fhm. I thougth the member enableMcsSync in taliseFhmMode_t struct  set to 1 will be worked for hopping . And the most important reason is that I need more than 1000 hops per second, if I re-run the full init sequence, It must be out of my requirement.

    I also found if I just exit the async chip's FHM mode (full exit), its tow channels will be synced again. I viewed the topic:FHM Calibration Resolution, I think exiting FHM will cause the calibration and tracking functions to re-run, that cause their phase re-sync again. But from exit  to enter fhm and vice versa will consume a lot of time, especially the commands of the three chips need to be transmitted in sequence by SPI.

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