ADRV9009 RF-SOM multichip sync

1. For JESD bring up its recommended to use single shot sysref, Continious also should work.

For RF phase sync The syref should reach both ADRV9009 and FPGA at same time.

2. Are you using multiple clock chips or same chip supplies clock to all 3 devices. ?

  Above diagram is not clear. Are you using evaluation board or custom board.

3. At every boot you need to run RF PLL phase sync and it should bring the phase to same value as shown in user guide,

1. I use continuous sysref to bring up JESD, it is ok. "The syref should reach both ADRV9009 and FPGA at same time", it means in one device clock cycle or exactly time, how the delay time between them and the jitters affect the RF phase sync? I use eval board (AD9528 inside), AD9528 is only used to bypass sysref, I can't measure the sysref signal from Ad9528 to ADRV9009.

2. I use 1 hmc7044 to generate clocks (for FPGA, AD9528, ADRV9009 refclk) and 2 hmc7044 to bypass them. The Sysref is generated from refclk and trigger.

3. Each board is in independent power-up sequence, are the sysref signals in all boards independent too? 

1. If the sync signal has skew , then the elastic buffer size can vary from boot to boot which impacts the phase of input signal. RF Phase sync will not be able to correct this,

2. for RF MCS to work properly , the device clock reaching both ADRV9009 should be aligned. RF PLL phase sync synchronizes internal LO to the device clock. If there is constant skew between devices you will some difference between devices which you can calibrate out during Antenna phase calibration (external).

3. Power up sequence can be different . Sysref timing is critical.

Thank for your answers,

According to the picture, all ADRV9009 enable MCS at the same time? Is it right?

Thank for your answers,

According to the picture, all ADRV9009 enable MCS at the same time? Is it right?

The picture above is for one channel of one transceiver over multiple boot up.with respect to a constant Device clock input (plot in comparison with device clock).

For each transceiver we need to ensure that the device clock reaches at same time. RF PLL phase sync adjusts the phase of LO to this input clock and ensures that the phase is aligned. So it is not necessary that you do MCS at the same time. When ever MCS is done each chip synchronizes itself to the reference clock and since same reference clock is used , the relative phase between different transceivers as well get aligned.

What the demand of the sysref frequency? I use  1MHz continuous sysref, RF PLL what is multiple of 1MHz is synchronized, but when sysref is 8MHz, it's not true. When I use 1 shot sysref to enable MCS, RF PLL is synchronized with all LO frequencies.

We recomend Sysref to be less than or equal to device clock /64. Below post has details.

https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/119010/adrv9009-sysref/371676#371676

Thanks for your help.

What about this (Vindod: on Mar 5, 2020 5:26 AM in reply to JV-IE)
https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/121260/lane-latency/361869#361869

It depends on how many deframers are used. If you are using single deframer at FPGA you need to run simultaneously. If they are different framers/ deframers then you can send it sequentially or simultaneously.

How does this answer relates to the configuration vietnguyen is using?

Comment was Generic , Looks like Vietnguyen using separate FPGA's for each ADRV9009.

So for Vietnguyen he use separate deframers at the FPGA. So he has to run the mcs sequences simultaneously. Which is not possible in a continuous sysref mode and without a central sysref distribution.

In his block diagram there is only a central devl_clk distribution. Which result in miss alligned LMFC clocks.

Yes correct.