adrv9009 multichip sync

Question

Hello, 
 I try to synchronize 2 ADRV9009 boards. I use Kintex Ultrascale FPGA and HMC7044 EVA board to generate reference clock and sysref signal. AD9528's outputs to ADRV9009/FPGA are distributed from VCXO, sysref signals to ADRV9009/FPGA are from external. 
 I see in Multichip Sync section of User Guide that two ADRV9009's device clocks and sysref signals are from only 1 AD9528. Is my structure possible? I connect 1 TX to 4 RX, 2 RX signals in TX's board is stable, other RX are not stable. Please give me some advice. 
 Thanks.

PVALAVAN · Accepted Answer

The phase will not be constant across frequency. 
 There could be some picosecond delay between two ADRV9009 and hence the phase variation may change with frequency. You can do a antenna calibration and find the phase variation across frequency and correct that in baseband.)

Vinod · Answer

We have provision in ADRV9009 evaluation board to share Sysref and Dev clock to second board. Please refer this post, https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/105981/two-adrv9009-eval-boards-on-zcu102 
 In your case there are three PLL-VCO circuits, there will be some phase mismatch over time because of 3 different VCO's. (the drift with time and temp may not be same for all 3). So It is recommended to try above mentioned option. 
 One thing you can try is to make sure that Dev clk reaching both ADRV9009 and FPGA are at same time. You can adjust delays available with AD9528 and HMC chip for that. Still not sure what accuracy you will get from this setup.

Popular Forums

Product Forums

Application Forums

Design Center Forums

Highlighted Webinar

Places

Libraries

Upcoming Learning & Events

Challenge Yourself!

What's Brewing

Places

Resources

Visit ContentZone

The Latest Read

New Release

Recent Technical Insights

Products Mentioned

Thread Details

adrv9009 multichip sync

Thread Summary