adrv9009 multichip sync

Can you please check the MCS status?

Hope you have enabled the RF Phase Sync option. Are you seeing phase variation boot to boot?

Can you please share more details on the measurements?. 

I use mode RF phase sync init and continuous tracking. Mcs status is ok (Reg value is 0x0B).

Ref clocks for ADRV are from AD9528's VCXO, they are synchronised. I enable sysref signal after both ADRVs have been enable MCS mode.

I set Baker 13 code in TX. After divider, RF signal goes to 2 RX in 2 different boards. RX signal in the board, which does not have TX, is not stable. LO frequency is 3GHz. I wonder the LOs in 2 boards are not synchronized.

We have provision in ADRV9009 evaluation board to share Sysref and Dev clock to second board. Please refer this post, https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/105981/two-adrv9009-eval-boards-on-zcu102

In your case there are three PLL-VCO circuits, there will be some phase mismatch over time because of 3 different VCO's. (the drift with time and temp may not be same for all 3). So It is recommended to try above mentioned option.

One thing you can try is to make sure that Dev clk reaching both ADRV9009 and FPGA are at same time. You can adjust delays available with AD9528 and HMC chip for that. Still not sure what accuracy you will get from this setup.

I try the case: ref_clk and sys_ref of 2 adrv9009 are from 1 ad9528. Outputs are synchronized at LO frequency = N* ref_clk with N is integer and not synchronized with N is fractional.

Am I wrong somewhere?

If you have enabled RF phase sync option , it should work.

when you say 

vietnguyen said:

not synchronized with N is fractional.

RF phase is not synchronised for LO frequency using fractional words? what offset are you seeing between and integer frequency and next fractional frequency? 

I check mcs status is 0x0b, so CLKPLL SDM is not sync. 

Adrv9009 has 3 PLLs, they are synchronized at the same time, aren't they? 

 In my case, I  connect 1 TX to 1 RX in same board and 1 RX in other board. Ref_clk is 245.76MHz,

+ LO 3GHz: 2 RX phases in 2 board are not same in different power up time.

+ LO 2,94912GHz: 2 RX phases are same in different power up time.

vietnguyen said:

I try the case: ref_clk and sys_ref of 2 adrv9009 are from 1 ad9528. Outputs are synchronized at LO frequency = N* ref_clk with N is integer and not synchronized with N is fractional.

What is the API version you are using? 

vietnguyen said:

I try the case: ref_clk and sys_ref of 2 adrv9009 are from 1 ad9528. Outputs are synchronized at LO frequency = N* ref_clk with N is integer and not synchronized with N is fractional.

What is the API version you are using? 

Arm version is 6.0.2. I use newest no-os library and modify it to fit with my project.

Can you please confirm what is the API version?

https://github.com/analogdevicesinc/no-OS/blob/master/drivers/rf-transceiver/talise/api/talise_version.h

https://github.com/analogdevicesinc/no-OS/tree/master/drivers/rf-transceiver/talise

Thank you,

API version is 3.6.0.5. 

Ref_clk signals are synchronised. Sys_ref signals come to ADRVs at same time, continuous and phases are constanst.

Mcs status is 0x0b.

Sync mode is init and conTrack.

 Procedure after power up:

- ad9528 initialize (off sysRef)

- adrv initialize

- getPllsLockStatus

- enableMultichipSync(1,&mcsstatus)

- on sysref

- enableMultichipSync(0,&mcsstatus)

- initArm

- loadStreamFromBinary

- loadArmFromBinary

- verifyArmCheckSum

- setRfPllFrequency

- getPllsLockstatus

- runInitCals

- waitInitCals

- config jesd204

- enableTrackingCals

- radioOn

- enable TX and RX

What can I do to solve the problem?

vietnguyen said:

+ LO 3GHz: 2 RX phases in 2 board are not same in different power up time

What is the relative phase difference you are measuring from boot to boot?

How is the Tx phase synchronization between the two ADRV9009?

RX phase difference is random value.

I haven't measured TX phase. I think if RF PLLs are synchronized, both TX and RX are synchronized. Is it true?

vietnguyen said:

I haven't measured TX phase. I think if RF PLLs are synchronized, both TX and RX are synchronized. Is it true?

Yes , same LO is used for Tx and Rx and RF phase sync adjust the Sigma delta modulator phase to have same phase as Ref_CLK.

How are you measuring Rx phase from 2 different ADRV9009 boards. ? 

If Tx is phase synced then Rx should also maintain same phase. 

Have you tried enabling tracking cal as well. ? ( TAL_RFPLLMCS_INIT_AND_CONTTRACK = 3) 

I connect 1 TX to 2 RX by a divider. The RX data is sent from 1 FPGA to the other by MGT transceivers. Compare 2 signal, I calculate the different phase.

I have tried enable TAL_RFPLLMCS_INIT_AND_CONTTRACK and other sync mode, but the same results.

I tried one shot SysRef mode, the different phase is constant now. In case, I generate Sysref from PLL2 of AD9528 1st, Sysref bypass in Ad9528 2nd, are Sysref signals in final ports not same phase? So mcs is not successful?

Thank you guys.

What was the sysref frequency you were using in continuous sysref mode?

For continuous sysref mode, you would need to make sure the sysref frequency is less than sampleRate/32 (or div 64 to be safer).

Are you seeing RF Phase sync for both integer and fractional RF PLL  frequency set with one shot Sysref mode?

I set The SysRef frequency = ref_clk/32.

In one shot mode, RX different phase is const for each frequency (both integer and fractional RF_PLL) from boot to boot. Can the phase be constant with all frequency? 

I change frequency, the RX different phase will change even when I set RfPhaseSyncMode = InitAndConTrack.