ADRV9009 sysref

Please refer to MULTICHIP SYNCHRONIZATION section of UG-1295.

For proper synchronization, the rising edge of SYSREF must be received at each device during the same device clock cycle. It is
recommended to disable the SYSREF, enable multichip sync, and then reenable the SYSREF signal. The SYSREF signal can either be
issued in individual pulses or be free running. If a periodic pulse is used, the phase must not change between rising edges. Single pulse
mode can be implemented by gating a free running SYSREF after the falling edge to prevent runt pulses.

But as described in the same datasheet " When multichip sync is enabled, the function is performed in four stages; each one is initiated with a rising SYSREF edge. The first two
SYSREF rising edges synchronize the device clock dividers. This portion of the synchronization requires some amount of time for the clock PLL outputs to settle". Do i correct understand if I will use free running SYSREF signal clock PLL outputs will continously re-synchronize?

For continuous sysref mode, you would need to make sure the sysref frequency is less than sampleRate/32 (or div 64 to be safer). This should be OK after issuing EnableMultichipSync(1) command and then stop MCS state machine using EnableMultichipSync(0). This would reset and synchronize the counters. You can read back the MCS state to confirm if its set correctly.

Thank you.

Hi Sir,

Would you please highlight that why sysref frequency is less than sampleRate/32 ( or div 64 to be safer) ?

Regards,

Manish

Hi Sir,

Would you please highlight that why sysref frequency is less than sampleRate/32 ( or div 64 to be safer) ?

Regards,

Manish

This required to meet the timing requirement of MCS process.

Hi Sir,

Could you explain a bit about timing requirement in MCS ? I didn't find anything related to this.  Kindly help

Regards,

Manish

The first SYSREF pulse resets the device clock divider, which causes the clock phase-locked loop (PLL) to relock. There is a required wait period before any further SYSREF pulses are registered. The wait period is set to 1,024 phase frequency detector (PFD) reference clock periods.

Sysref frequency less than sampleRate/32 ( or div 64 to be safer) is required to meet the wait period.

 From user guide - 1295,

When multichip sync is enabled, the function is performed in four stages; each one is initiated with a rising SYSREF edge. The first two SYSREF rising edges synchronize the device clock dividers. This portion of the synchronization requires some amount of time for the clock PLL outputs to settle. The third SYSREF rising edge synchronizes the high speed digital clock dividers. The fourth SYSREF rising edge synchronizes the numerically controlled oscillators (NCOs), the JESD204B LMFC, and the RF PLL phase synchronization.

mcs sequencing is a 12 step procedure. https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/adrv9009.c#L1139

If you’re just interested in achieving JESD deterministic latency across multiple devices.  Continuously is just fine.

Synchronize other state machines inside the RF transceiver. One of those is very likely the RF SYNC feature where you synchronize the RF PLLs. This step requires that all ADRV9009 need to capture exactly the same sysref pulse. I don't see options how you can fix this issue with sysref pulses in a continuous mode.