Dear Sir,
As UG-1295, initial calibrations include of "RX_phase_correction" which is design to keep Rx path phase constant with gain changing. Thanks.
1.Would you kind to update the maximum of deviation for full gain change once the correction is disable or enable respectively ?
2.Meanwhile, there are four chips co-work with FPGA on our system, the same reference clock source 30.72MHz with AD9528 , if any the reference design for the clock tree of SYSREF & REF_CLK between ADRV9009, AD9528, and FPGA, so that the multi-chips of ADRV9009 with JESD204B DATA and RF phase can sync well as it should be.
