Is there a digital loopback mode for the ADRV9009?

No There is no digital loop back.

For JESD debugging , you can use the PRBS Generator for framer and PRBS checker for deframer. Details are given in User Guide UG- 1295.

The typical usage sequence is as follows:

1. Initialize the device as outlined in the Link Establishment section.
2. Run the TALISE_enableFramerTestData() with the required framer, set the test data source to the desired PRBS order, and set the injection point to serializer input.
3. Enable the PRBS checker on the BBP and reset its error count.
4. Wait a specific amount of time to allow a good number of samples to be transmitted, and then check the PRBS error count of the BBP.

hi,

 There are a few questions to ask. 

1.how to enable the PRBS checker on the BBP and reset its error count? Are there any examples ?

2.The BBP is PL(FPGA)?or PS(ARM)?I think it's PL,but I can't find how to configure FPGA with API.whether you can show some advise.

For BBP , please contact your FPGA vendor from where you purchased JESD IP. If using ADI JESD IP please post your queries in the FPGA forum. (https://ez.analog.com/fpga)

 Please refer to our reference design for more details.

https://wiki.analog.com/resources/eval/user-guides/adrv9009/reference_hdl