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Two ADRV9009 EVAL Boards on ZCU102

Hi Support,

I want to use two ADRV9009 Eval Boards on ZCU102.

ZCU102 has two FMC(HPC) connectors.

Is it possible to run two ADRV9009 Eval Boards?

Synchronization of  data between two ADRV9009 chips will be OK?

Best Regards.


  • Please refer to the below post: 

    Refer to the RFPLL phase synchronization section in UG for more details on MCS.

  • Hi Srimoyi and Tobe,

    The given URL just confirms that we can use 2 ADRV9009s on ZCU102, but does not mention about the data synchronization between 2 boards.

    In my case, I have built two separated versions - one ADRV9009 on HPC1 , the other on HPC0. Both version works flawlessly. But when combing them to create a version for 2 ADRV9009, it does not work anymore. JESD204 link cannot establish. I am investigating issues may cause this problem.

    For data synchronization between 2 boards, I think they should be sourced from a common clock source for device clock and SYSREF. Do you have any further constraint for 2-boards synchronization?

    Best Regards,

    Trung Nguyen

  • Please refer USer guide UG 1295 section on RF PLL Phase Synchronization Demo Setup with 2 Two Evaluation Platforms

  • Hello Vinod,

    many thanks for your reference. Somehow I skipped that part.

    I would like to ask you some questions regarding the clock scheme.

    As in the below picture - UG1295

    sysref and refclk (device clock), which are generated from AD9528 of an eval board are provided to all devices.

    - As reviewing from the schematic, there is no way to provide SYSREF and REFCLK directly to ADRV9009 from OFFBOARD DEVICES. Signals still have to go through AD9528. That's why I come up with the below clock scheme.

    Could you kindly review it?

    However, I have some doubts here:

    1. What are the input pins for REFCLK on AD9528?

    2. How does REFCKL bypass all PLL or logics to reach to ADRV9009?

    Since in datasheet of AD9528, there is no such path for REFCLK. There exists a path for SYSREF as in below picture

    Thanks in advance,

    Trung Nguyen

  • In this case you can skip the second AD9528 and take out sysref and devclk from first AD9528 via the schematic snapshot you copied above and feed directly to next AD9371.

    Any of the 14 outputs of AD9528 can be configured as Refclock

  • Hi Vinod,

    thank so much for your help.

    As in your reply, I rechecked the schematic. It is possible to feed off-board dev_clk and system directly to ADRV9009 as the following pictures.

    Output 5 {J404, J405}, Output7 {J406, J407} or Output8 {J408, J409} are used to output devclk and sysref from the AD9528 of the first evaluation board.

    • dev_clk is then feed to the ADRV9009 on second board through port J410, J411
    • sysref through J412 and J413


    Thanks in advance,

    Trung Nguyen

  • Yes Correct. There will be some DNI which you need to populate and may be remove few components to disconnect existing clocks.

  • Hello Vinod,

    Everything is clear. Thanks for supports.

    Trung Nguyen

  • is it really ok to skip the second AD9528? Would the second AD9528 still provide SYSREF/REFCLK to the FPGA side? In other words : can the SYSREF/REFCLK for the FPGA side come from 1 PLL, and the SYSREF/REFCLK for the ADRV9009 side come from 2 different PLLS?  (which do have the same ref clock I guess, but still it looks a bit tricky?)

  • Hello,

    In my case, the followingis my setup (I am testing it)

    - The second AD9528 doesn't provide REFCLK to FPGA. REFCLK is taken from the first AD9528. But it needs to route from the first board to the second board, then to FPGA through FMC port (to provide REF for GT Transceiver)

    - SYSREF for AD9009 on the second board, on the other hand, is still provided by the second AD9528 (in bypass mode - source is from 1st AD9528), then I can adjust its delay.

    - SYSREF for FPGA side just need to be taken from 1st AD9528.

    P/S: I think you should start another thread, so we can discuss further and get more support from ADI.


    Trung Nguyen