Products Mentioned

ADRV9009 Recommended for New Designs
The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital...
Datasheet
ADRV9009 on Analog.com

AD9528 Recommended for New Designs
The AD9528 is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator for multiple device synchronization. The first stage phase-locked loop...
AD9528 on Analog.com

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Clock tree for multiple ADRV9009 ICs

		
	
				

			

									
					    RajatRao
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Aug 20, 2018 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
		    			
    
			    
    Hello,
    
 
    I have a design with 8 ADRV9009 ICs. AD9528 is the clock chip used and it provide clocks and SYSREF ADRV9009 and the FPGA GT banks. We need all ADRV9009 ICs to have phase sync so the clock inputs must all be aligned.
    
 
    These 8 ICs are present on one radio card. There are 4 such cards in the system, so the an input GLOBAL CLK is fed into each card.
    
 
    Below are two possible clocking schemes, which is better/suggested?
    
			
    
			
									
		                             
                        

    
    
                                            
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                on Aug 21, 2018 4:25 AM
            
            
						
			            		
        
		
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        Thanks for the reply.
        
 
          
  1. Since the input clock to the AD9528 is a clean clock, I'm actually bypassing both PLLs. The input clock to the AD9528 is fed into the VCXO input pins. Is this the correct way of using it as a buffer?
 
        
 
          
  2. Yes, I think option 1 can be used with 2x AD9528. But, what is the timing requirement for the forwarded clock from the first AD9528 to the second one. I can adjust the delays to offset any mismatch in the length matching on the PCB, but how do I measure the offset on the fly?
 
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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                on Aug 21, 2018 4:25 AM
            
            
						
			            		
          
		
										0
					
	
          

		
		
          
		
          
                                
                                                            
          
					
          Thanks for the reply.
          
 
            
  1. Since the input clock to the AD9528 is a clean clock, I'm actually bypassing both PLLs. The input clock to the AD9528 is fed into the VCXO input pins. Is this the correct way of using it as a buffer?
 
          
 
            
  2. Yes, I think option 1 can be used with 2x AD9528. But, what is the timing requirement for the forwarded clock from the first AD9528 to the second one. I can adjust the delays to offset any mismatch in the length matching on the PCB, but how do I measure the offset on the fly?
 
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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