Products Mentioned

ADRV9009 Recommended for New Designs
The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital...
Datasheet
ADRV9009 on Analog.com

AD9528 Recommended for New Designs
The AD9528 is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator for multiple device synchronization. The first stage phase-locked loop...
AD9528 on Analog.com

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Clock tree for multiple ADRV9009 ICs

		
	
				

			

									
					    RajatRao
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Aug 20, 2018 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
		    			
    
			    
    Hello,
    
 
    I have a design with 8 ADRV9009 ICs. AD9528 is the clock chip used and it provide clocks and SYSREF ADRV9009 and the FPGA GT banks. We need all ADRV9009 ICs to have phase sync so the clock inputs must all be aligned.
    
 
    These 8 ICs are present on one radio card. There are 4 such cards in the system, so the an input GLOBAL CLK is fed into each card.
    
 
    Below are two possible clocking schemes, which is better/suggested?
    
			
    
			
									
		                             
                        

    
    
                                            
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                 Clock Generation and Distribution
                
                                                    
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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Aug 21, 2018 4:08 AM
            
            
						
			            		
      
		
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      Option 1 will be better. One AD9528 has 14 outputs. " The AD9528 can also be used as a dual input flexible buffer to distribute 14 device clock and/or SYSREF signals "
      
 
      So for 8 Transceiver + FPGA you need only 2 AD9528. For second AD9528 you can bypass PLL2 to avoid offset because of second VCO.
      
 
      You can adjust the delay in first AD9528 such that all the DEV_CLK's (from both AD9528) are reaching the transceiver at same time.
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Aug 21, 2018 4:08 AM
            
            
						
			            		
      
		
										0
					
	
      

		
		
      
		
      
                                
                                                            
      
					
      Option 1 will be better. One AD9528 has 14 outputs. " The AD9528 can also be used as a dual input flexible buffer to distribute 14 device clock and/or SYSREF signals "
      
 
      So for 8 Transceiver + FPGA you need only 2 AD9528. For second AD9528 you can bypass PLL2 to avoid offset because of second VCO.
      
 
      You can adjust the delay in first AD9528 such that all the DEV_CLK's (from both AD9528) are reaching the transceiver at same time.
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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