Hello,
I have a design with 8 ADRV9009 ICs. AD9528 is the clock chip used and it provide clocks and SYSREF ADRV9009 and the FPGA GT banks. We need all ADRV9009 ICs to have phase sync so the clock inputs must all be aligned.
These 8 ICs are present on one radio card. There are 4 such cards in the system, so the an input GLOBAL CLK is fed into each card.
Below are two possible clocking schemes, which is better/suggested?
In both options, AD9528 is used only for fanout in PLL bypass mode.
In option 1, 4 AD9528 ICs are used (instead of 3) to make placement and routing easier and convenient. The advantage of option 1 is that layout is simplified. In option 2, the symmetric placement of the input stage AD9528 is a bit difficult.
The problem with option 1 is that I don't know what are the timing requirements for the forwarded clocks. The clocks that go to the radio ICs and the FPGA should be length matched for phase sync and the SYSREF should meet timing. But what about the forwarded clocks. To what should they be length matched, what are the timing requirements to ensure that all ADRV9009 ICs are in sync.
Which option is better, 1 or 2?
In both options, AD9528 is used only for fanout in PLL bypass mode.
In option 1, 4 AD9528 ICs are used (instead of 3) to make placement and routing easier and convenient. The advantage of option 1 is that layout is simplified. In option 2, the symmetric placement of the input stage AD9528 is a bit difficult.
The problem with option 1 is that I don't know what are the timing requirements for the forwarded clocks. The clocks that go to the radio ICs and the FPGA should be length matched for phase sync and the SYSREF should meet timing. But what about the forwarded clocks. To what should they be length matched, what are the timing requirements to ensure that all ADRV9009 ICs are in sync.
Which option is better, 1 or 2?
