Support ADRV9008x/ADRV9009

Q&A

by SongSunHah
Support ADRV9008x/ADRV9009

Started 2 days ago
45 0 0
Not Answered
Production Testing Image Issue of ADRV2CRR-FMC and ADRV9009-ZU11EG 0
Not Answered

Hi, I have some problems when testing the ADRV2CRR-FMC+ADRV9009-ZU11EG EVB: First problem is that the latest production testing image file can't be extracted successfully after many times of trying, would you please help to check it? The version is...

software 2022 adrv9009 software defined radio ADRV9009-ZU11EG rf and microwave Show More

45 0 0
by oijn
Support ADRV9008x/ADRV9009

Started 5 days ago
30 0 0
Not Answered
Question on JESD Alignment Character Selection – Why K28.5? 0
Not Answered

Hi team, I am currently working with JESD-based high-speed data converters and had a conceptual question regarding the choice of alignment/control characters used within the protocol. Specifically, I would like to understand why the K28.5 character...

jesd jesd204 vivado 2018.3 software jesd204b adrv9009 software defined radio transceivers rf and microwave Show More

30 0 0
by Sidra2026
Support ADRV9008x/ADRV9009

Started 5 days ago
51 0 0
Not Answered
ADRV9009 JESD204B Testbench Build Issues on ZCU102 — HDL 2022_R2 0
Not Answered

I am building the HDL and testbench repositories for the JESD204B interface framework targeting the ADRV9009 project on the ZCU102 evaluation board. HDL Repository The HDL repository has been built successfully using tag version 2022_R2 . Reference...

Vivado 2022.2 software ADRV9009-ZCU102 testbench software defined radio High Speed A/D Converters >10 MSPS rf and microwave Show More

51 0 0
by tcachat
Support ADRV9008x/ADRV9009

Latest 5 days ago by tcachat
1660 36 0
Not Answered
I/Q data mixed up in JESD? +1
Not Answered

We have a custom board with an ADRV9009. After power up and configuration, we face rarely strange RF output (less than 1/10 times). On the scope it seems that one I/Q sample over 2 is delayed by about 30 samples. So that samples are coming in the following...

jesd software adrv9009 TES3.6.2.1 Wideband Transceiver IC RF Integrated Transceivers Show More

1660 36 0
by benbenmumu
Support ADRV9008x/ADRV9009

Started 11 days ago
34 0 0
Not Answered
tx_adxcvr: adxcvr_drp_wait_idle: Timeout! 0
Not Answered

I got an error when using the adrv9009 no_os program: tx_adxcvr: adxcvr_drp_wait_idle: Timeout!ERR: ../src/platform/xilinx_transceiver.c:141:xilinx_xcvr_drp_read(): xilinx_xcvr_drp_read: Failed to read reg 16-0x0014: -1 hardware information: FPGA is XCZU19EG...

software Clock ICs clock and timing adrv9009 software defined radio rf and microwave 3.6.5 Show More

34 0 0
by shane4
Support ADRV9008x/ADRV9009

Latest 12 days ago by shane4
95 1 0
Not Answered
RF Phase Synchronization Steps 0
Not Answered

I have a adrv9009-zu11eg SOM using pyadi-iio im investigating phase coherence between all 4 receive channels. I have TX setup to transmit a tone, which is fed to a splitter and into the 4 RX channels on the SOM. I'm following a version of the script here...

software adrv9009 software defined radio phase coherence ADRV9009-ZU11EG rf and microwave Show More

95 1 0
by UVLSIDRIVER
Support ADRV9008x/ADRV9009

Latest 19 days ago by vanitha
123 1 0
Not Answered
Issue with "adxcvr_clk_enable()" in SDK reference design 0
Not Answered

Hi, I am trying to run the NO-OS reference design in ADRV9009 where I am getting an error stating "error: rx_adxcvr: adxcvr_clk_enable() failed". My sampling rate and clock rates are 245.76MHz, Rx Lane Rate is 9.8304GHz, ORx lane rate is 4.9152GHz, Tx...

vivado 2018.3 software Clock ICs clock and timing sdk2018.3 adrv9009 software defined radio rf and microwave Show More

123 1 0
by mukunthan
Support ADRV9008x/ADRV9009

Latest 1 month ago by danmois
255 5 0
Answered
CPLL RX buffer underflow error, CPLL RX buffer overflow error +1
Answered

Hi danmois I’m currently facing a CPLL elastic buffer overflow and underflow issue , and because of this, the link status is unstable — it intermittently switches between CGS and DATA states. Here are the system details for reference: FPGA:...

adrv9008-1 software GTHE3 transceiver VITIS adrv9009 microblaze receiver vivado Vivado 2023.2 Vitis 2023.2 Wideband Transceiver IC RF Integrated Transceivers Show More

255 5 0
by UVLSIDRIVER
Support ADRV9008x/ADRV9009

Latest 1 month ago by UVLSIDRIVER
208 5 0
Not Answered
Issue with Serializer Lane Crossbar Configuration – ADRV9009 JESD Initialization Stuck at CGS 0
Not Answered

Hello, We are facing an issue related to the serializer lane crossbar configuration in the ADRV9009. System Description: We are using a custom ADRV9009 board. The SERDIN pins from the ADRV9009 are routed to the FPGA without any lane swap...

vivado 2018.3 software sdk2018.3 adrv9009 Wideband Transceiver IC RF Integrated Transceivers Show More

208 5 0
by UVLSIDRIVER
Support ADRV9008x/ADRV9009

Latest 1 month ago by UVLSIDRIVER
176 2 0
Answered
Intermittent RX Data Glitches and PRBS31 Errors on Custom ADRV9009 Board (184.32 MHz Profile) +1
Answered

Hello, We are using a custom board based on the ADRV9009 and operating with a 184.32 MHz profile (profile files are attached). We are facing an issue during JESD204 link initialization. Both RX and TX links successfully reach DATA state, and the link...

Clock Generation Devices Clock Generation and Distribution vivado 2018.3 software sdk2018.3 adrv9009 Wideband Transceiver IC RF Integrated Transceivers Show More

176 2 0
by UVLSIDRIVER
Support ADRV9008x/ADRV9009

Latest 1 month ago by vanitha
432 9 0
Not Answered
JESD204 TX Initialization Intermittently Fails on Power-Up but Recovers After Reinit 0
Not Answered

Hello, We are using two ADRV chips on our custom hardware and using the FMCOMMS8 RTL and SDK from the ADI GitHub repository. We are facing an intermittent JESD204 TX link status issue during power-up. We have tried multiple approaches to resolve it...

vivado 2018.3 software sdk2018.3 adrv9009 Wideband Transceiver IC RF Integrated Transceivers Show More

432 9 0
by faith529
Support ADRV9008x/ADRV9009

Latest 1 month ago by vanitha
93 1 1
Not Answered
Hello，I would like to know if the signal of ADRV9008 is overloaded.Which register is used to obtain the signal overload flag of ADRV9008. 0
Not Answered

Hello，I would like to know if the signal of ADRV9008 is overloaded.Which register is used to obtain the signal overload flag of ADRV9008. Thank you.

hardware

93 1 1
by oldeng
Support ADRV9008x/ADRV9009

Latest 1 month ago by vanitha
190 1 0
Answered
ADRV9009 NO-OS IIO ADC DATA looks weired 0
Answered

I build the no-os project with iio_enable and it can be connected the first couple frames look normal after few frame the adc data capture looks weired I understand the uart speed is too low for transmit adc data. is this normal or there is...

software Vivado 2022 adrv9009 Wideband Transceiver IC RF Integrated Transceivers Show More

190 1 0
by julims
Support ADRV9008x/ADRV9009

Latest 1 month ago by vanitha
205 3 0
Not Answered
adrv9009zu11eg connect to TES 0
Not Answered

Hi, I have an ADRV9009zu11eg and would like to connect to the TES software to load custom configurations. the problem is: the default port seems not working and the Ip connection is correct since i'm using for ssh and loading files to the board...

tes hardware adrv9009 adrv9009zu11EG Wideband Transceiver IC RF Integrated Transceivers Show More

205 3 0
by oldeng
Support ADRV9008x/ADRV9009

Latest 2 months ago by vanitha
356 4 0
Not Answered
ADRV9009 NO-OS problem 0
Not Answered

I design a board with xczu15eg+adrv9009 there is a known hardware problem on my schematic . the syncin+ and syncin- is reverse but I notice the datasheet say the syncin pin is optional.when unuse it can be connect to ground. so I connect it...

software adrv9009 Wideband Transceiver IC RF Integrated Transceivers

356 4 0

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Q&A

Not Answered
Production Testing Image Issue of ADRV2CRR-FMC and ADRV9009-ZU11EG 0
Not Answered

Not Answered
Question on JESD Alignment Character Selection – Why K28.5? 0
Not Answered

Not Answered
ADRV9009 JESD204B Testbench Build Issues on ZCU102 — HDL 2022_R2 0
Not Answered

Not Answered
I/Q data mixed up in JESD? +1
Not Answered

Not Answered
tx_adxcvr: adxcvr_drp_wait_idle: Timeout! 0
Not Answered

Not Answered
RF Phase Synchronization Steps 0
Not Answered

Not Answered
Issue with "adxcvr_clk_enable()" in SDK reference design 0
Not Answered

Answered
CPLL RX buffer underflow error, CPLL RX buffer overflow error +1
Answered

Not Answered
Issue with Serializer Lane Crossbar Configuration – ADRV9009 JESD Initialization Stuck at CGS 0
Not Answered

Answered
Intermittent RX Data Glitches and PRBS31 Errors on Custom ADRV9009 Board (184.32 MHz Profile) +1
Answered

Not Answered
JESD204 TX Initialization Intermittently Fails on Power-Up but Recovers After Reinit 0
Not Answered

Not Answered
Hello，I would like to know if the signal of ADRV9008 is overloaded.Which register is used to obtain the signal overload flag of ADRV9008. 0
Not Answered

Answered
ADRV9009 NO-OS IIO ADC DATA looks weired 0
Answered

Not Answered
adrv9009zu11eg connect to TES 0
Not Answered

Not Answered
ADRV9009 NO-OS problem 0
Not Answered

Q&A

Not Answered Production Testing Image Issue of ADRV2CRR-FMC and ADRV9009-ZU11EG 0 Not Answered

Not Answered Question on JESD Alignment Character Selection – Why K28.5? 0 Not Answered

Not Answered ADRV9009 JESD204B Testbench Build Issues on ZCU102 — HDL 2022_R2 0 Not Answered

Not Answered I/Q data mixed up in JESD? +1 Not Answered

Not Answered tx_adxcvr: adxcvr_drp_wait_idle: Timeout! 0 Not Answered

Not Answered RF Phase Synchronization Steps 0 Not Answered

Not Answered Issue with "adxcvr_clk_enable()" in SDK reference design 0 Not Answered

Answered CPLL RX buffer underflow error, CPLL RX buffer overflow error +1 Answered

Not Answered Issue with Serializer Lane Crossbar Configuration – ADRV9009 JESD Initialization Stuck at CGS 0 Not Answered

Answered Intermittent RX Data Glitches and PRBS31 Errors on Custom ADRV9009 Board (184.32 MHz Profile) +1 Answered

Not Answered JESD204 TX Initialization Intermittently Fails on Power-Up but Recovers After Reinit 0 Not Answered

Not Answered Hello，I would like to know if the signal of ADRV9008 is overloaded.Which register is used to obtain the signal overload flag of ADRV9008. 0 Not Answered

Answered ADRV9009 NO-OS IIO ADC DATA looks weired 0 Answered

Not Answered adrv9009zu11eg connect to TES 0 Not Answered

Not Answered ADRV9009 NO-OS problem 0 Not Answered

Not Answered
Production Testing Image Issue of ADRV2CRR-FMC and ADRV9009-ZU11EG 0
Not Answered

Not Answered
Question on JESD Alignment Character Selection – Why K28.5? 0
Not Answered

Not Answered
ADRV9009 JESD204B Testbench Build Issues on ZCU102 — HDL 2022_R2 0
Not Answered

Not Answered
I/Q data mixed up in JESD? +1
Not Answered

Not Answered
tx_adxcvr: adxcvr_drp_wait_idle: Timeout! 0
Not Answered

Not Answered
RF Phase Synchronization Steps 0
Not Answered

Not Answered
Issue with "adxcvr_clk_enable()" in SDK reference design 0
Not Answered

Answered
CPLL RX buffer underflow error, CPLL RX buffer overflow error +1
Answered

Not Answered
Issue with Serializer Lane Crossbar Configuration – ADRV9009 JESD Initialization Stuck at CGS 0
Not Answered

Answered
Intermittent RX Data Glitches and PRBS31 Errors on Custom ADRV9009 Board (184.32 MHz Profile) +1
Answered

Not Answered
JESD204 TX Initialization Intermittently Fails on Power-Up but Recovers After Reinit 0
Not Answered

Not Answered
Hello，I would like to know if the signal of ADRV9008 is overloaded.Which register is used to obtain the signal overload flag of ADRV9008. 0
Not Answered

Answered
ADRV9009 NO-OS IIO ADC DATA looks weired 0
Answered

Not Answered
adrv9009zu11eg connect to TES 0
Not Answered

Not Answered
ADRV9009 NO-OS problem 0
Not Answered