Design Support ADRV9008-1/ADRV9008-2/ADRV9009

Q&A

by robertoqu
Design Support ADRV9008-1/ADRV9008-2/ADRV9009

Started 11 hours ago
23 0 0
Not Answered
Lane sharing on ADRV9009 - Clock sharing between two AD-FMCOMMS8-EBZ boards 0
Not Answered

I have experience in FPGA but new to SDR and apologize if making dumb questions. I am defining parts for an 8-channel MIMO prototype device and planning to use two AD-FMCOMMS8-EBZ boards and an AMD Kria K26 on a custom carrier. The total bit rate from...

Clock Generation Devices Datasheet/Specs Clock Generation and Distribution Clock Synchronization ad-fmcomms8-ebz adrv9009 lane sharing Wideband Transceiver IC RF Integrated Transceivers Show More

23 0 0
by ghwrk
Design Support ADRV9008-1/ADRV9008-2/ADRV9009

Latest 20 days ago by vanitha
59 1 0
Not Answered
Download initCal results for fastlock performan 0
Not Answered

I am controlling the ADRV9009 from an FPGA, while the hopRfPll option allows retuning, I was wondering if it was possible to initialise all frequencies, download the results from their initCals, and then reprogram them at a later time (akin to the process...

hardware hopping adrv9009 Wideband Transceiver IC RF Integrated Transceivers Show More

59 1 0
by anshum
Design Support ADRV9008-1/ADRV9008-2/ADRV9009

Latest 22 days ago by CapotaBianca
520 9 0
Answered
ADRV9009-ZCU106 no-OS (headless_arm.c) – TALISE_verifySpiReadWrite() fails at scratchpad write +2
Answered

Hi, I am bringing up the ADRV9009 FMC board on the ZCU106 using the standard no-OS project from the Analog Devices GitHub (Vitis, 2023.2). I am using the headless_arm.c application file without any custom modifications. When I run the code, I consistently...

software no-OS repo 2023.2 adrv9009 Talise no-os Wideband Transceiver IC RF Integrated Transceivers Show More

520 9 0
by sunny123
Design Support ADRV9008-1/ADRV9008-2/ADRV9009

Latest 1 month ago by vanitha
130 1 0
Not Answered
How to enable DC offset tracking calibration in IIO Oscilloscope (ZCU102 + ADRV9009) 0
Not Answered

Hello, I’m using a ZCU102 and ADRV9009 evaluation board to test functionality and performance. While checking some signals using IIO Oscilloscope, I noticed a signal at the center that looks like DC offset. The attached screenshot shows the signal...

Clock Generation and Distribution hardware adrv9009 Wideband Transceiver IC RF Integrated Transceivers Show More

130 1 0
by UVLSIDRIVER
Design Support ADRV9008-1/ADRV9008-2/ADRV9009

Latest 1 month ago by vanitha
153 1 0
Not Answered
ADRV9009 – xcvr clock enable failed when using 200 MHz or 400 MHz TX bandwidth profiles 0
Not Answered

Hello, I am currently using the ADRV9009 evaluation board with a custom FPGA board based on XC7Z045-FFG676-2. My setup uses Vivado 2021.2 and VITIS 2021.2, with reference projects on the ADI GitHub repository. The provided reference design includes...

Vivado 2021.2 software adrv9009 vitis 2021.2 Wideband Transceiver IC RF Integrated Transceivers Show More

153 1 0
by Arehman
Design Support ADRV9008-1/ADRV9008-2/ADRV9009

Latest 1 month ago by vanitha
150 1 0
Not Answered
ADRV9009: Two-Tone Generation Using FPGA NCO and TDD Support for ADRV9008-1/2 0
Not Answered

Hello, I am working with the ADRV9009 transceiver and would like to confirm a few points: Is it possible to generate two different RF signals on the two TX paths using a common LO (for example LO = 4.5 GHz), if I perform a digital frequency shift...

baseband Datasheet/Specs adrv9008-1 adrv9008-2 adrv9009 Digital Offset digital signal Wideband Transceiver IC RF Integrated Transceivers Show More

150 1 0
by studyandlook
Design Support ADRV9008-1/ADRV9008-2/ADRV9009

Latest 1 month ago by vanitha
555 2 0
Not Answered
adrv9009 0
Not Answered

Hello Referring to the formula for calculating the lane rate on page 38 of document UG-1295, I want to change the default TX lane rate from 2457.6Mhz to 1228.8Mhz and the default RX rate from 4915.2Mhz to 1228.8Mhz. How should I configure this?The FPGA...

software Wideband Transceiver IC RF Integrated Transceivers

555 2 0
by YaduS
Design Support ADRV9008-1/ADRV9008-2/ADRV9009

Latest 1 month ago by vanitha
122 1 0
Not Answered
Register Map document for ADRV9008-1 0
Not Answered

Hi, I'm integrating the ADRV9008-1 with a Xilinx KU115 FPGA via custom RTL for SPI/ JESD communication, without using a soft processor like MicroBlaze due to high resource consumption concerns. The datasheets and UG-1295 manual don't include a direct...

xilinx Datasheet/Specs adrv9008-1 adrv9009 ADRV9008-1W/PCBZ transceivers Wideband Transceiver IC reciever fpga RF Integrated Transceivers Show More

122 1 0
by epiqDaniel
Design Support ADRV9008-1/ADRV9008-2/ADRV9009

Latest 2 months ago by travisfcollins
152 2 0
Not Answered
Generating 80Msps/64Mhz Profile in Profile Configuration Wizard 0
Not Answered

I have attempted to generate a profile with the following settings have had issues when running it. The ADRV9002 gui has the traffic light for valid profiles but I wasn't sure if there was any indication for invalid profiles on ADRV9009. Any comments...

hardware software v2.5 adrv9009 Wideband Transceiver IC RF Integrated Transceivers Show More

152 2 0
by maurizio.sonzogni@abe.it
Design Support ADRV9008-1/ADRV9008-2/ADRV9009

Latest 4 months ago by maurizio.sonzogni@abe.it
702 17 0
Answered
ADRV9008-2 at 491.52MSPS cannot set RF frequency below 280MHZ +1
Answered

I'm using ADRV9008-2 at 491.52 MSPS for TX and ORX. I'm working on ZCU102 + ADRV9008-2 W/PCBZ boards, with no-OS firmware. This is workink fine if I set the RF frequency to 280MHz and above. If I set the RF frequency at 270MHz I get this consle output...

software adrv9008-2 491.52MSPS RF Frequency Wideband Transceiver IC RF Integrated Transceivers Show More

702 17 0

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Q&A

Not Answered
Lane sharing on ADRV9009 - Clock sharing between two AD-FMCOMMS8-EBZ boards 0
Not Answered

Not Answered
Download initCal results for fastlock performan 0
Not Answered

Answered
ADRV9009-ZCU106 no-OS (headless_arm.c) – TALISE_verifySpiReadWrite() fails at scratchpad write +2
Answered

Not Answered
How to enable DC offset tracking calibration in IIO Oscilloscope (ZCU102 + ADRV9009) 0
Not Answered

Not Answered
ADRV9009 – xcvr clock enable failed when using 200 MHz or 400 MHz TX bandwidth profiles 0
Not Answered

Not Answered
ADRV9009: Two-Tone Generation Using FPGA NCO and TDD Support for ADRV9008-1/2 0
Not Answered

Not Answered
adrv9009 0
Not Answered

Not Answered
Register Map document for ADRV9008-1 0
Not Answered

Not Answered
Generating 80Msps/64Mhz Profile in Profile Configuration Wizard 0
Not Answered

Answered
ADRV9008-2 at 491.52MSPS cannot set RF frequency below 280MHZ +1
Answered

Q&A

Not Answered Lane sharing on ADRV9009 - Clock sharing between two AD-FMCOMMS8-EBZ boards 0 Not Answered

Not Answered Download initCal results for fastlock performan 0 Not Answered

Answered ADRV9009-ZCU106 no-OS (headless_arm.c) – TALISE_verifySpiReadWrite() fails at scratchpad write +2 Answered

Not Answered How to enable DC offset tracking calibration in IIO Oscilloscope (ZCU102 + ADRV9009) 0 Not Answered

Not Answered ADRV9009 – xcvr clock enable failed when using 200 MHz or 400 MHz TX bandwidth profiles 0 Not Answered

Not Answered ADRV9009: Two-Tone Generation Using FPGA NCO and TDD Support for ADRV9008-1/2 0 Not Answered

Not Answered adrv9009 0 Not Answered

Not Answered Register Map document for ADRV9008-1 0 Not Answered

Not Answered Generating 80Msps/64Mhz Profile in Profile Configuration Wizard 0 Not Answered

Answered ADRV9008-2 at 491.52MSPS cannot set RF frequency below 280MHZ +1 Answered

Not Answered
Lane sharing on ADRV9009 - Clock sharing between two AD-FMCOMMS8-EBZ boards 0
Not Answered

Not Answered
Download initCal results for fastlock performan 0
Not Answered

Answered
ADRV9009-ZCU106 no-OS (headless_arm.c) – TALISE_verifySpiReadWrite() fails at scratchpad write +2
Answered

Not Answered
How to enable DC offset tracking calibration in IIO Oscilloscope (ZCU102 + ADRV9009) 0
Not Answered

Not Answered
ADRV9009 – xcvr clock enable failed when using 200 MHz or 400 MHz TX bandwidth profiles 0
Not Answered

Not Answered
ADRV9009: Two-Tone Generation Using FPGA NCO and TDD Support for ADRV9008-1/2 0
Not Answered

Not Answered
adrv9009 0
Not Answered

Not Answered
Register Map document for ADRV9008-1 0
Not Answered

Not Answered
Generating 80Msps/64Mhz Profile in Profile Configuration Wizard 0
Not Answered

Answered
ADRV9008-2 at 491.52MSPS cannot set RF frequency below 280MHZ +1
Answered