Integration of Default HDL Project and Default no-OS Project for ADRV9002:
- As per the Analog Devices user guide, I downloaded the Xilinx Vivado 2021.2 (2021_R2) HDL reference design from the official GitHub repository.
- Following the user guide, I successfully generated the .xsa file from the Vivado HDL design. The Figure shown below for generating the Bit-file and exporting the hardware through .xsa file.
3. To build the no-OS project, I followed the processor configuration specified by Analog Devices and completed the build process using the Xilinx Build Prerequisites described in the no-OS Build Guide. The link provides (link No-OS Build Guide — no-OS documentation).
4.The no-OS project was built successfully without any build errors.
5.However, when I attempted to debug the application using JTAG, I observed that the JTAG communication became extremely slow, making the debugging process impractical. As a result, I am unable to debug the application successfully.
6.Additionally, it was observed that entering debug mode takes a significant amount of time. After the debugger initializes, the error shown in the figure below is encountered.
Issue:
- Why is the JTAG debugging process extremely slow after integrating the default HDL project and the default no-OS project for the ADRV9002?
- What could be the possible causes and recommended solutions for this issue?
- After starting the debug session, the following error is displayed: "Failed to reset Device and set SPI Config”??