Unused Pins in SPI Mode

HI,

We will get back to you.

Regards

Rahul

Hello,
I'm a little confused. Is there a reason you’re not using AGPIO to control the external LNA? The standard TES approach for external LNA gain control is to drive the LNA state using AGPIO outputs based on the gain table. In contrast, RX1_EN and RX2_EN are dedicated RX channel enable pins from the nevassa itself not the FPGA. How exactly are you using these pins to control an external LNA?

Thank you for the response and the suggestion to use the GPIO pins. I think I was unclear in my description of the problem, and I think we might be dealing with an existing board, where signal routing is fixed. I believe what they've done is connected outputs from their FPGA to both the RX1/2_EN and the enable pins for the LNA. In this architecture, the external LNA is enabled at the same time the RX channel is enabled. Regardless, can you describe the behavior of the SPI pins when the chip is in pin control mode? Thank you for your continued assistance.

Hello,

I'm sorry for the delay in getting back to you. We don't have a way to test this particular question. Have you tried testing your design and noticed any issues. 

Best, Aubrey

We have not, but fortunately, there was time for a new spin of the board and they were able to revise the design to take advantage of the GPIO pins. Thanks for the suggestion on that one!