RX tuning failure for ADRV9002

Hi everyone,

We have a custom board with ADRV9002 and are at the stage where calibrations pass but tuning fails.

The HDL is based on the zcu102 project provided by AD (2023_R2). It has been modified (pin assignments) to work for our board. Similarly, the software is based on the 2023_R2 branch, also provided by AD.

We've enabled `DEBUG` in the source code and see a lot of debug information however haven't pin-pointed the issue yet (not sure if the fault is in HDL, software, hardware, config file).

Below is a snippet of the timing matrix when RX1 tuning is being attempted:

May 29 18:57:16 zynqmp kernel: adrv9002 spi1.0: DEBUG-TUNE: Completed clk/data scan, generating result matrix
May 29 18:57:16 zynqmp kernel: SAMPL CLK: 1000000 tuning: RX1
May 29 18:57:16 zynqmp kernel: 0:1:2:3:4:5:6:7
May 29 18:57:16 zynqmp kernel: 0:# # # # # # # #
May 29 18:57:16 zynqmp kernel: 1:# # # # # # # #
May 29 18:57:16 zynqmp kernel: 2:# # # # # # # #
May 29 18:57:16 zynqmp kernel: 3:# # # # # # # #
May 29 18:57:16 zynqmp kernel: 4:# # # # # # # #
May 29 18:57:16 zynqmp kernel: 5:# # # # # # # #
May 29 18:57:16 zynqmp kernel: 6:# # # # # # # #
May 29 18:57:16 zynqmp kernel: 7:# # # # # # # #
May 29 18:57:16 zynqmp kernel: adrv9002 spi1.0: DEBUG-TUNE: Stopping test
May 29 18:57:16 zynqmp kernel: adrv9002 spi1.0: cfg test stop:1, ssi:2, c:0, tx:0
May 29 18:57:16 zynqmp kernel: adrv9002 spi1.0: DEBUG-TUNE: Test stopped successfully
May 29 18:57:16 zynqmp kernel: adrv9002 spi1.0: DEBUG-TUNE: Field matrix for analysis:
May 29 18:57:16 zynqmp kernel: adrv9002 spi1.0: DEBUG-TUNE: Clk 0: 1 1 1 1 1 1 1 1
May 29 18:57:16 zynqmp kernel: adrv9002 spi1.0: DEBUG-TUNE: Clk 1: 1 1 1 1 1 1 1 1
May 29 18:57:16 zynqmp kernel: adrv9002 spi1.0: DEBUG-TUNE: Clk 2: 1 1 1 1 1 1 1 1
May 29 18:57:16 zynqmp kernel: adrv9002 spi1.0: DEBUG-TUNE: Clk 3: 1 1 1 1 1 1 1 1
May 29 18:57:16 zynqmp kernel: adrv9002 spi1.0: DEBUG-TUNE: Clk 4: 1 1 1 1 1 1 1 1
May 29 18:57:16 zynqmp kernel: adrv9002 spi1.0: DEBUG-TUNE: Clk 5: 1 1 1 1 1 1 1 1
May 29 18:57:16 zynqmp kernel: adrv9002 spi1.0: DEBUG-TUNE: Clk 6: 1 1 1 1 1 1 1 1
May 29 18:57:16 zynqmp kernel: adrv9002 spi1.0: DEBUG-TUNE: Clk 7: 1 1 1 1 1 1 1 1

We recently forced the tuning to pass just to see what happens next and saw that the tuning for TX1/TX2 passes (but fails for RX2 again).

May 29 18:57:17 zynqmp kernel: SAMPL CLK: 1000000 tuning: TX2
May 29 18:57:17 zynqmp kernel: 0:1:2:3:4:5:6:7
May 29 18:57:17 zynqmp kernel: 0:# o o o o o o o
May 29 18:57:17 zynqmp kernel: 1:o # # o o o o o
May 29 18:57:17 zynqmp kernel: 2:o o # o o o o o
May 29 18:57:17 zynqmp kernel: 3:o o o # o o o o
May 29 18:57:17 zynqmp kernel: 4:o o o o # o o o
May 29 18:57:17 zynqmp kernel: 5:o o o o o # o o
May 29 18:57:17 zynqmp kernel: 6:o o o o o o # o
May 29 18:57:17 zynqmp kernel: 7:o o o o o o o #
May 29 18:57:17 zynqmp kernel: adrv9002 spi1.0: DEBUG-TUNE: Stopping test
May 29 18:57:17 zynqmp kernel: adrv9002 spi1.0: cfg test stop:1, ssi:2, c:1, tx:1

Another point to note is that for RX/TX, we have the polarity inverted for some signals (I and Q are always opposite polarity, see json file snippet). We've reflected that in the config file (.json) but would be good to receive some confirmation/validation about that.

"rxSsiConfig": {
"ssiType": 2,
"ssiDataFormatSel": 4,
"numLaneSel": 1,
"strobeType": 0,
"lsbFirst": 0,
"qFirst": 0,
"txRefClockPin": 0,
"lvdsIBitInversion": true,
"lvdsQBitInversion": false,
"lvdsStrobeBitInversion": false,
"lvdsUseLsbIn12bitMode": 0,
"lvdsRxClkInversionEn": true,
"cmosDdrPosClkEn": false,
"cmosClkInversionEn": false,
"ddrEn": true,
"rxMaskStrobeEn": false
}

What else should we look at to narrow down this problem? How should we approach testing when we are not sure where the shortcoming is (HDL, hardware, software?) Any pointers will help!

Thanks!