No TX output signal (ADRV9002/ZCU102, no-OS, DMA_DEMO)

Hello!

Could you let us know which HDL branch or release you are using?

Regards,

Elena

Hello,

no-OS:

On branch main
Your branch is up to date with 'origin/main'.

git rev-parse HEAD
502129359e223ede53bbe8587892f10c4de09ed3

HDL:

On branch hdl_2022_r2
Your branch is up to date with 'origin/hdl_2022_r2'

git rev-parse HEAD
ae6e248f219a5bb2e63733c762e9561c072d037e

Thanks!

Ilya

Hello!

To avoid potential incompatibilities between Vivado and Vitis, could you please try using the following HDL branch: hdl_2023_r2 with Vivado 2023.2?

After rebuilding, please let us know if you still encounter the problem.

Hello,

I think there is a HDR/no-OS compatibility issue.

Without any changes to the no-OS code and HDL branch: hdl_2023_r2 with Vivado 2023.2 

there is an interface tuning error:

Hello
ERR: ../noos/drivers/rf-transceiver/navassa/adrv9002.c:2341:adrv9002_init(): Interface tuning failed: -5
adrv9002_post_setup() failed with status -5

With NO_OS_LOG_LEVEL changed to debug NO_OS_LOG_DEBUG:

DEBUG: Tx1 SSI clk driven by RX1 REF
DEBUG: Tx2 SSI clk driven by RX2 REF
DEBUG: RX1 enabled
DEBUG: RX2 enabled
DEBUG: TX1 enabled
DEBUG: TX2 enabled
DEBUG: pos: 15, Chan1:1BE5F7, Chan2:1BE5F7DEBUG: cfg test stop:0, ssi:2, c:0, tx:0
DEBUG: Set intf delay clk:0, d:0, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:0, d:1, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:0, d:2, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:0, d:3, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:0, d:4, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:0, d:5, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:0, d:6, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:0, d:7, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:1, d:0, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:1, d:1, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:1, d:2, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:1, d:3, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:1, d:4, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:1, d:5, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:1, d:6, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:1, d:7, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:2, d:0, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:2, d:1, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:2, d:2, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:2, d:3, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:2, d:4, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:2, d:5, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:2, d:6, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:2, d:7, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:3, d:0, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:3, d:1, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:3, d:2, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:3, d:3, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:3, d:4, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:3, d:5, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:3, d:6, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:3, d:7, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:4, d:0, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:4, d:1, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:4, d:2, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:4, d:3, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:4, d:4, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:4, d:5, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:4, d:6, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:4, d:7, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:5, d:0, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:5, d:1, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:5, d:2, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:5, d:3, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:5, d:4, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:5, d:5, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:5, d:6, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:5, d:7, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:6, d:0, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:6, d:1, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:6, d:2, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:6, d:3, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:6, d:4, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:6, d:5, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:6, d:6, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:6, d:7, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:7, d:0, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:7, d:1, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:7, d:2, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:7, d:3, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:7, d:4, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:7, d:5, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:7, d:6, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: Set intf delay clk:7, d:7, tx:0 c:0
DEBUG: pn error in c:0, reg: 02
DEBUG: cfg test stop:1, ssi:2, c:0, tx:0
ERR: ../noos/drivers/rf-transceiver/navassa/adrv9002.c:2341:adrv9002_init(): Interface tuning failed: -5
adrv9002_post_setup() failed with status -5

Thanks,

Ilya

Hello!

We are looking into this and will get back to you.

Regards,

Elena

Hello,

I have not received any updates.

I tried multiple combinations of no-OS and HDL releases but even the ones that don't exhibit interface turning errors don't produce any TX output.

When ZCU102 is booted from the Linux SD card I programmed from the ADI recommended image file ((kernel 4.14.0 !) . TES 0.29.0 is not able to connect as it claims that the device is up but does not have enough disk space. TES 0.27.0 connects only after multiple software restarts. Neither one allows to change the device IP address (when it is changed in GUI the software is still trying to connect to 192.168.1.10).

TES 0.27.0 configuration can be programmed and there is TX output but any exported by TES device profile is rejected by no-OS. It does not accept configurations with TX and RX interface rates mismatched.

With this fixed there is a much longer error.

I'd like the thread to be elevated to the customer support group that can really help resolving the issues.

Thanks,

Ilya

Hi,

There are two workflows on our side. One for open source and one for evaluation.
The TES works with the evaluation version.
The public one is based on Kuiper Linux and no-OS, the TES will not directly work with the public ones.
You can define a configuration through TES, save the profile as .json and use it later.
For public Linux you can load the profile after the system boots through libiio (IIO oscilloscope or python).
For no-OS you have to convert the profile. you can do it with this bash script. Then replace the .h files for CMOS or LVDS profiles.
Also, make sure the HDL you have is built for LVDS or CMOS and the no-OS is configured for that interface.

It looks like both no-OS and HDL are default to CMOS.
projects: adrv9001: Add LVDS flag · analogdevicesinc/no-OS@bb4f105
hdl/projects/adrv9001/zcu102/system_project.tcl at main · analogdevicesinc/hdl

Andrei

Hello!

Do you want to build the project for LVDS or CMOS?

If you want to build for CMOS, you can follow the steps below:

1. Download the ZIP archive for your project (for example, adrv9001.zip) from the latest no-OS release. Inside the archive you will find multiple folders with different configurations, as described in this JSON file. Each configuration includes a BOOT.BIN, and a separate tar archive with the sources used to generate it.

1. Prepare an SD card formatted as FAT32 and copy the desired BOOT.BIN (based on the configuration you want to use) into the first partition.
2. Insert the SD card and configure the board to boot from SD.
3. Connect the UART cable, open a serial terminal (e.g., Tera Term), and set the baud rate to 115200.
4. Power on the system.

If you use the BOOT.BIN example that includes IIO Oscilloscope support for CMOS (adrv9001_xilinx_iio_adrv9002_adrv9001_zcu102), you should see an output similar to this in the serial terminal:

Next, open IIO Oscilloscope, select the correct serial port and baud rate shown in the terminal output, press Refresh, and then Connect.

In the DAC Data Manager window, configure the frequency, scale, and phase as shown here:

If you want to build the project for LVDS, you need to build both the HDL project with the LVDS flag (make CMOS_LVDS_N=0) and the no-OS project with the LVDS option (make LVDS=y IIOD=y) to generate the correct BOOT.BIN. After that, follow the same steps starting from step 2

If you also want to run the dma_example for LVDS (as you did before), you can plot the received data by following the instructions here: DMA_EXAMPLE demo [Analog Devices Wiki]

Regards,

Elena

Hi DASHTechIC !

Do you have any updates? Did you manage to solve your issues?

Regards,

Elena

Closed due to inactivity.