Hi,
I want to specify some of the parameters of AGC. Working an adrv every day I would like to know exactly what should I wait from each parameter. For the questions below I used the guide in the link:
www.analog.com/.../adrv9001-ug1828.pdf
1) Working either with fast attack/ recovery or not, the guide says that after the gain change, by applying a certain gain index, the counter of the detector resets. Does this happen to all the detectors? For example, let's say I work with APD,HB and Power detector. Every detector has a counter limit. Now let's say that each one of the upper limit is equal to 5. At some time the counters are equal to: APD=6 HB=4 PD=7. Following the priority scheme of AGC a gain attack will happen, based on the APD overload. After the attack what are there values are equal to? APD=0 and HB=4 AND PD=6? Clarify to me what's happening.
2) PARAMETER: peak_wait_time: Number of gain control clock cycles to wait before enabling peak detectors after a gain change. Is this only for peak detectors? If so, peak wait time defines time only after a gain change or does apply for initial time needed for the detectors to start counting? When are the detectors start counting?
3)PARAMETER: slowLoopSettlingDelay :In the guide is claimed that: Number of AGC clock cycles to wait after a gain change before the AGC changes gain again. I have two questions about this:
- Is there a SLS delay before the first gain change by AGC? For example if an APD calls for an overrange for the first time will AGC wait a certain number of clock cycles (SLS) or does this apply after the 1st declair.
- The guide says: Number of AGC clock cycles to wait after a gain change before the AGC changes gain again. Let's assume a gain change happens by AGC but the APD is still calling overrange. In the forum it says that after the gain change the counter resets and for the APD to call an overrange again the counts must be exceeded again, that leads us to the conclusion that the second gain attack doesn't happen simultaneously. How is it possible to define the number of AGC cycles for a second attack to happen when at the same time the counter of the detector must be exceeded again? If I say SLS=5 AGC cycle, and the counter is exceeded at 3 AGC cycle (APD counts peaks as AGC cycles in which the signal overloads not actual peaks) what is going to happen? I provide links from the forum relative to this question:
4)PARAMETER: enableSyncPulseForGainCounter: In the guide says: Allows synchronization of AGC gain update counter to the time-slot boundary. My question is what is this time slot referred to?
5) What does hboverloadpowermode does exactly?
6) In the guide it is claimed that after the ADC there is the 1st decimation block. After the 1st decimation block the digital dtaa have frequency equal to 184.32MHz (Page 156). Is that valid? If so, does that mean that HB and Power detector receive data approximately every 5.43ns? If I configure the number of samples of power detector by defining powermeasurementduration (PMD) am I configuring which of the received data I am going to use for power measurement? How does power detector and HB work actually?
Thank you
Jonatha
Edit Notes
Questions for AGC parameters[edited by: Jonatha at 8:24 AM (GMT -5) on 4 Feb 2026]
