Inverted FMC polarity

lf22222

on Jan 18, 2026

Thread Summary

The user encountered issues porting the ZCU102 + ADRV9002 reference design to a custom devkit using the TE0701 carrier and TE0820 SOM, due to swapped differential pairs and poor skew/length matching. The solution involved inverting the polarity in HDL using IBUFDS_DIFF_OUT and hard-coding delay values to compensate for the skew, which allowed interface tuning to pass. The user also confirmed that the internal termination circuits in the ADRV9002 do not need to be enabled, as they are already enabled in the FPGA.
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Category: Hardware

Hey all, I'm porting over the ZCU102 + ADRV9002 reference design to a custom devkit (and then down the line to a custom board). I'm using the TE0701 carrier with the TE0820 SOM. The issue is, some of the FMC differential pairs connect to the IOs with swapped polarity. I initially tried updating the constraints file to reflect how it's physically wired, but Vivado won't let me do that as it actually does check if the physical pin's polarity matches when you use IBUFDS/OBUFDS. So next I tried updating the constraints as if the polarity was correct and just inverting in HDL, but that did not seem to work (interface tuning fails). I also know that the SSI config lets you flip ~some~ signals. But in a previous forumn post it was noted you cant flip RX I/Q individually, only TX.

The following are flipped on my devkit: fpga_mcs_in, rx1_idata_in, rx1_strobe_in, tx1_dclk_out, tx2_strobe_out.

What's the correct way to go about porting the reference design in this case? Where should the polarity be corrected?

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AubreyTarmu

on Jan 19, 2026 10:45 AM
0
Hello,

you are correct you have limited ability to flip the signals in the API, the manual is not ambigious.

...

Let me look into this for you, but a couple of follow up questions first,

1) What was the original reason that made you want to flip the bits?

2) Did you correctly terminate the output in your design for the adrv9001 fmc
3) Can you send me a constraints file & schematic?
4) How exactly are you inverting the adrv9001 polarity in FPGA? Can you send your model?
5) Is this test w/ Linux, NO-OS, or TES?

6) Which HDL are you using for this?
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lf22222
on Jan 19, 2026 5:15 PM in reply to AubreyTarmu
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Just following up, I found the official pinout for the Trenz board.
PDF
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AubreyTarmu

on Jan 21, 2026 3:50 PM in reply to lf22222
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Hello,
1) to clarify when you say the below two are swapped you don't mean you are using a separate constraints file than what you just shared where you have those pins actually swapped? This is your current active constraints correct?
2) A lot of the issues we see with interface tuning is related to improper termination (either adding an extra 100 ohm resistor, or not adding one at all). I looked at your schematic, for A1/A2 looking for an extra resistor but the link you sent me keeps crashing now, so I would recommend looking at the schematic again to see if they added an extra resistor.
3) I'm very confused why you decided to flip it in both the HDL & in the json kernel settings can you elaborate on that decision? It seems you should be able to get away with just flipping the input and outputs in the HDL, but I see you have done quite a bit of logic in your HDL, do you mind explaining if your HDL changes are there to do more than just invert?

Best, Aubrey
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lf22222
on Jan 21, 2026 4:56 PM in reply to AubreyTarmu
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1.) Yeah thats the active constraints file, theres no separate one. So for example, in the pcb its routed rx1_idata_in_n -> G1, rx1_idata_in_n -> F1. It's flipped in the constraints file so Vivado doesn't complain.

2.) Yeah double checked the schematics, neither the som nor the carrier has physical termination. The FMC directly connects to the IO banks through the B2B connectors. Is there any configuration needed to enable the internal termination circuits in the ADRV? Already have them enabled in the FPGA.

3.) I'll try again but do it all in HDL. The reason I mixed and matched is because the tx ones were easier to do in json, guess thats over complicated. Yeah all my change does is invert, it's just a lot of boilerplate because I made it a top level parameter I can configure in Vivado GUI.

I additionally wanted to ask what the significance of the bottom left LED is. I notice on the ZCU102 it's green (the smaller left one). Maybe this is a clue?
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AubreyTarmu

on Jan 22, 2026 3:46 PM in reply to lf22222
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Hello,

Is there any configuration needed to enable the internal termination circuits in the ADRV? Already have them enabled in the FPGA.

No

what the significance of the bottom left LED is.

It means you're failing vadj_test, you need to have the voltage at 1.8v. Do you have it set to 1.8v? The part will not work without that LED on.
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lf22222
on Jan 26, 2026 1:39 PM in reply to AubreyTarmu
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Hey Aubrey, I do have 1.8v, it's set via a dip switch. When I use a barebones vivado design (no adrv and no fmc configuration), just the zynqmp block, the LED is in fact on. But it's off when using my modified design for the adrv9001. Should be noted that I'm not an FPGA engineer, but is there anything constraints wise that could cause this? The vadj setting should be external to the fpga on this devkit.

Thanks!
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lf22222

on Jan 26, 2026 8:26 PM in reply to lf22222

I believe I have fixed the issue? Do these logs indicate it's operating nominally:

[    1.856409] axi_sysid 85000000.axi-sysid-0: [adrv9001] [LVDS] on [trenz] git branch <main> git <c23b17c33112b0c3f31e2f48ad0e654677993771> dirty [2026-01-27 00:31:20] UTC
[   17.121915] platform 84a00000.axi-adrv9002-rx-lpc: deferred probe pending: (reason unknown)
[   17.121948] platform 84a0c800.axi-adrv9002-core-tdd-lpc: deferred probe pending: (reason unknown)
[   17.121963] platform 84a02000.axi-adrv9002-tx-lpc: deferred probe pending: (reason unknown)
[   28.478717] adrv9002 spi1.0: Tx1 SSI clk driven by RX1 REF
[   28.478755] adrv9002 spi1.0: Tx2 SSI clk driven by RX2 REF
[   28.497431] adrv9002 spi1.0: RX1 enabled
[   28.497470] adrv9002 spi1.0: RX2 enabled
[   28.497486] adrv9002 spi1.0: TX1 enabled
[   28.497502] adrv9002 spi1.0: TX2 enabled
[   28.497518] adrv9002 spi1.0: pos: 15, Chan1:1BE5F7, Chan2:1BE5F7
[   32.018014] adrv9002 spi1.0: Requesting warmboot coefficients: "Navassa_LVDS_init_cals.bin"n
[   33.170848] adrv9002 spi1.0: Set dpgio: 2, signal: 1
[   33.171283] adrv9002 spi1.0: Set dpgio: 1, signal: 0
[   33.171704] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
[   33.171727] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
[   33.171749] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
[   33.171766] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
[   33.171785] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
[   33.171843] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
[   33.182168] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 30720000 Hz
[   33.182193] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 30720000 Hz
[   33.182217] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:0
[   33.183579] adrv9002 spi1.0: Set intf delay clk:0, d:0, tx:0 c:0
[   33.191162] adrv9002 spi1.0: Set intf delay clk:0, d:1, tx:0 c:0
[   33.198581] adrv9002 spi1.0: Set intf delay clk:0, d:2, tx:0 c:0
[   33.206015] adrv9002 spi1.0: Set intf delay clk:0, d:3, tx:0 c:0
[   33.212863] adrv9002 spi1.0: Set intf delay clk:0, d:4, tx:0 c:0
[   33.220257] adrv9002 spi1.0: Set intf delay clk:0, d:5, tx:0 c:0
[   33.227659] adrv9002 spi1.0: Set intf delay clk:0, d:6, tx:0 c:0
[   33.235123] adrv9002 spi1.0: Set intf delay clk:0, d:7, tx:0 c:0
[   33.242584] adrv9002 spi1.0: Set intf delay clk:1, d:0, tx:0 c:0
[   33.250054] adrv9002 spi1.0: Set intf delay clk:1, d:1, tx:0 c:0
[   33.258300] adrv9002 spi1.0: Set intf delay clk:1, d:2, tx:0 c:0
[   33.266504] adrv9002 spi1.0: Set intf delay clk:1, d:3, tx:0 c:0
[   33.274632] adrv9002 spi1.0: Set intf delay clk:1, d:4, tx:0 c:0
[   33.282794] adrv9002 spi1.0: Set intf delay clk:1, d:5, tx:0 c:0
[   33.290994] adrv9002 spi1.0: Set intf delay clk:1, d:6, tx:0 c:0
[   33.299321] adrv9002 spi1.0: Set intf delay clk:1, d:7, tx:0 c:0
[   33.309329] adrv9002 spi1.0: Set intf delay clk:2, d:0, tx:0 c:0
[   33.318835] adrv9002 spi1.0: Set intf delay clk:2, d:1, tx:0 c:0
[   33.328198] adrv9002 spi1.0: Set intf delay clk:2, d:2, tx:0 c:0
[   33.337440] adrv9002 spi1.0: Set intf delay clk:2, d:3, tx:0 c:0
[   33.347178] adrv9002 spi1.0: Set intf delay clk:2, d:4, tx:0 c:0
[   33.357575] adrv9002 spi1.0: Set intf delay clk:2, d:5, tx:0 c:0
[   33.367337] adrv9002 spi1.0: Set intf delay clk:2, d:6, tx:0 c:0
[   33.377578] adrv9002 spi1.0: Set intf delay clk:2, d:7, tx:0 c:0
[   33.387776] adrv9002 spi1.0: Set intf delay clk:3, d:0, tx:0 c:0
[   33.397147] adrv9002 spi1.0: Set intf delay clk:3, d:1, tx:0 c:0
[   33.406779] adrv9002 spi1.0: Set intf delay clk:3, d:2, tx:0 c:0
[   33.417034] adrv9002 spi1.0: Set intf delay clk:3, d:3, tx:0 c:0
[   33.426543] adrv9002 spi1.0: Set intf delay clk:3, d:4, tx:0 c:0
[   33.435789] adrv9002 spi1.0: Set intf delay clk:3, d:5, tx:0 c:0
[   33.444999] adrv9002 spi1.0: Set intf delay clk:3, d:6, tx:0 c:0
[   33.454591] adrv9002 spi1.0: Set intf delay clk:3, d:7, tx:0 c:0
[   33.464675] adrv9002 spi1.0: Set intf delay clk:4, d:0, tx:0 c:0
[   33.474218] adrv9002 spi1.0: Set intf delay clk:4, d:1, tx:0 c:0
[   33.484084] adrv9002 spi1.0: Set intf delay clk:4, d:2, tx:0 c:0
[   33.493427] adrv9002 spi1.0: Set intf delay clk:4, d:3, tx:0 c:0
[   33.503045] adrv9002 spi1.0: Set intf delay clk:4, d:4, tx:0 c:0
[   33.513130] adrv9002 spi1.0: Set intf delay clk:4, d:5, tx:0 c:0
[   33.522781] adrv9002 spi1.0: Set intf delay clk:4, d:6, tx:0 c:0
[   33.533038] adrv9002 spi1.0: Set intf delay clk:4, d:7, tx:0 c:0
[   33.542488] adrv9002 spi1.0: Set intf delay clk:5, d:0, tx:0 c:0
[   33.552568] adrv9002 spi1.0: Set intf delay clk:5, d:1, tx:0 c:0
[   33.561937] adrv9002 spi1.0: Set intf delay clk:5, d:2, tx:0 c:0
[   33.571893] adrv9002 spi1.0: Set intf delay clk:5, d:3, tx:0 c:0
[   33.580854] adrv9002 spi1.0: Set intf delay clk:5, d:4, tx:0 c:0
[   33.590347] adrv9002 spi1.0: Set intf delay clk:5, d:5, tx:0 c:0
[   33.600308] adrv9002 spi1.0: Set intf delay clk:5, d:6, tx:0 c:0
[   33.609577] adrv9002 spi1.0: Set intf delay clk:5, d:7, tx:0 c:0
[   33.619272] adrv9002 spi1.0: Set intf delay clk:6, d:0, tx:0 c:0
[   33.629729] adrv9002 spi1.0: Set intf delay clk:6, d:1, tx:0 c:0
[   33.639594] adrv9002 spi1.0: Set intf delay clk:6, d:2, tx:0 c:0
[   33.649110] adrv9002 spi1.0: Set intf delay clk:6, d:3, tx:0 c:0
[   33.658757] adrv9002 spi1.0: Set intf delay clk:6, d:4, tx:0 c:0
[   33.668942] adrv9002 spi1.0: Set intf delay clk:6, d:5, tx:0 c:0
[   33.678591] adrv9002 spi1.0: Set intf delay clk:6, d:6, tx:0 c:0
[   33.688737] adrv9002 spi1.0: Set intf delay clk:6, d:7, tx:0 c:0
[   33.698314] adrv9002 spi1.0: Set intf delay clk:7, d:0, tx:0 c:0
[   33.708382] adrv9002 spi1.0: Set intf delay clk:7, d:1, tx:0 c:0
[   33.717871] adrv9002 spi1.0: Set intf delay clk:7, d:2, tx:0 c:0
[   33.727752] adrv9002 spi1.0: Set intf delay clk:7, d:3, tx:0 c:0
[   33.737056] adrv9002 spi1.0: Set intf delay clk:7, d:4, tx:0 c:0
[   33.746785] adrv9002 spi1.0: Set intf delay clk:7, d:5, tx:0 c:0
[   33.756842] adrv9002 spi1.0: Set intf delay clk:7, d:6, tx:0 c:0
[   33.766441] adrv9002 spi1.0: Set intf delay clk:7, d:7, tx:0 c:0
[   33.777912] adrv9002 spi1.0: cfg test stop:1, ssi:2, c:0, tx:0
[   33.779763] adrv9002 spi1.0: RX: Got clk: 0, data: 4
[   33.779917] adrv9002 spi1.0: Set intf delay clk:0, d:0, tx:1 c:0
[   33.797493] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   33.810962] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   33.811496] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   33.811556] adrv9002 spi1.0: Set intf delay clk:0, d:1, tx:1 c:0
[   33.826318] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   33.838976] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   33.839372] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   33.839419] adrv9002 spi1.0: Set intf delay clk:0, d:2, tx:1 c:0
[   33.855760] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   33.870020] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   33.870563] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   33.870624] adrv9002 spi1.0: Set intf delay clk:0, d:3, tx:1 c:0
[   33.888652] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   33.905047] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   33.905591] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   33.905651] adrv9002 spi1.0: Set intf delay clk:0, d:4, tx:1 c:0
[   33.924199] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   33.940476] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   33.941006] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   33.941066] adrv9002 spi1.0: Set intf delay clk:0, d:5, tx:1 c:0
[   33.958823] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   33.975877] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   33.976421] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   33.976481] adrv9002 spi1.0: Set intf delay clk:0, d:6, tx:1 c:0
[   33.994546] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.011485] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.012191] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.012252] adrv9002 spi1.0: Set intf delay clk:0, d:7, tx:1 c:0
[   34.030475] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.047298] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.047901] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.047962] adrv9002 spi1.0: Set intf delay clk:1, d:0, tx:1 c:0
[   34.065133] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.081407] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.081944] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.082002] adrv9002 spi1.0: Set intf delay clk:1, d:1, tx:1 c:0
[   34.100146] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.115396] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.116085] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.116146] adrv9002 spi1.0: Set intf delay clk:1, d:2, tx:1 c:0
[   34.134245] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.151011] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.151547] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.151607] adrv9002 spi1.0: Set intf delay clk:1, d:3, tx:1 c:0
[   34.169843] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.186277] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.186808] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.186867] adrv9002 spi1.0: Set intf delay clk:1, d:4, tx:1 c:0
[   34.198369] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.207291] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.207592] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.207628] adrv9002 spi1.0: Set intf delay clk:1, d:5, tx:1 c:0
[   34.216514] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.226328] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.226604] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.226641] adrv9002 spi1.0: Set intf delay clk:1, d:6, tx:1 c:0
[   34.234524] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.243355] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.243703] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.243747] adrv9002 spi1.0: Set intf delay clk:1, d:7, tx:1 c:0
[   34.252327] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.260586] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.260860] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.260885] adrv9002 spi1.0: Set intf delay clk:2, d:0, tx:1 c:0
[   34.269174] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.280248] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.280491] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.280515] adrv9002 spi1.0: Set intf delay clk:2, d:1, tx:1 c:0
[   34.287106] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.294408] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.294633] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.294658] adrv9002 spi1.0: Set intf delay clk:2, d:2, tx:1 c:0
[   34.301924] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.310213] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.310443] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.310467] adrv9002 spi1.0: Set intf delay clk:2, d:3, tx:1 c:0
[   34.317178] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.324344] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.324570] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.324593] adrv9002 spi1.0: Set intf delay clk:2, d:4, tx:1 c:0
[   34.331199] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.338438] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.338660] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.338685] adrv9002 spi1.0: Set intf delay clk:2, d:5, tx:1 c:0
[   34.345293] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.352445] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.352670] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.352694] adrv9002 spi1.0: Set intf delay clk:2, d:6, tx:1 c:0
[   34.359920] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.367562] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.367787] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.367861] adrv9002 spi1.0: Set intf delay clk:2, d:7, tx:1 c:0
[   34.375167] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.383362] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.383591] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.383615] adrv9002 spi1.0: Set intf delay clk:3, d:0, tx:1 c:0
[   34.391554] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.399326] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.399555] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.399579] adrv9002 spi1.0: Set intf delay clk:3, d:1, tx:1 c:0
[   34.407554] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.415628] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.415913] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.415937] adrv9002 spi1.0: Set intf delay clk:3, d:2, tx:1 c:0
[   34.423112] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.430880] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.431110] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.431134] adrv9002 spi1.0: Set intf delay clk:3, d:3, tx:1 c:0
[   34.438970] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.447037] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.447262] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.447286] adrv9002 spi1.0: Set intf delay clk:3, d:4, tx:1 c:0
[   34.455188] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.463371] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.463599] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.463623] adrv9002 spi1.0: Set intf delay clk:3, d:5, tx:1 c:0
[   34.471590] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.479335] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.479560] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.479583] adrv9002 spi1.0: Set intf delay clk:3, d:6, tx:1 c:0
[   34.487439] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.495230] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.495457] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.495481] adrv9002 spi1.0: Set intf delay clk:3, d:7, tx:1 c:0
[   34.502903] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.511072] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.511300] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.511324] adrv9002 spi1.0: Set intf delay clk:4, d:0, tx:1 c:0
[   34.519294] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.527475] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.527702] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.527726] adrv9002 spi1.0: Set intf delay clk:4, d:1, tx:1 c:0
[   34.534919] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.542646] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.542871] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.542895] adrv9002 spi1.0: Set intf delay clk:4, d:2, tx:1 c:0
[   34.550538] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.558428] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.558655] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.558678] adrv9002 spi1.0: Set intf delay clk:4, d:3, tx:1 c:0
[   34.566186] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.574033] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.574260] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.574284] adrv9002 spi1.0: Set intf delay clk:4, d:4, tx:1 c:0
[   34.581486] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.589167] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.589393] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.589417] adrv9002 spi1.0: Set intf delay clk:4, d:5, tx:1 c:0
[   34.596815] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.604483] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.604708] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.604731] adrv9002 spi1.0: Set intf delay clk:4, d:6, tx:1 c:0
[   34.611957] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.619552] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.619778] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.619839] adrv9002 spi1.0: Set intf delay clk:4, d:7, tx:1 c:0
[   34.626882] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.634842] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.635067] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.635091] adrv9002 spi1.0: Set intf delay clk:5, d:0, tx:1 c:0
[   34.642087] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.649881] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.650107] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.650130] adrv9002 spi1.0: Set intf delay clk:5, d:1, tx:1 c:0
[   34.657700] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.665477] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.665703] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.665727] adrv9002 spi1.0: Set intf delay clk:5, d:2, tx:1 c:0
[   34.673078] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.680765] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.680991] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.681015] adrv9002 spi1.0: Set intf delay clk:5, d:3, tx:1 c:0
[   34.687697] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.696011] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.696237] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.696261] adrv9002 spi1.0: Set intf delay clk:5, d:4, tx:1 c:0
[   34.703467] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.711220] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.711444] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.711468] adrv9002 spi1.0: Set intf delay clk:5, d:5, tx:1 c:0
[   34.719288] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.727270] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.727498] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.727521] adrv9002 spi1.0: Set intf delay clk:5, d:6, tx:1 c:0
[   34.735334] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.743077] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.743302] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.743326] adrv9002 spi1.0: Set intf delay clk:5, d:7, tx:1 c:0
[   34.751210] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.759382] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.759608] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.759632] adrv9002 spi1.0: Set intf delay clk:6, d:0, tx:1 c:0
[   34.767580] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.775840] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.776067] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.776091] adrv9002 spi1.0: Set intf delay clk:6, d:1, tx:1 c:0
[   34.782691] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.790420] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.790646] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.790670] adrv9002 spi1.0: Set intf delay clk:6, d:2, tx:1 c:0
[   34.798341] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.806287] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.806515] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.806538] adrv9002 spi1.0: Set intf delay clk:6, d:3, tx:1 c:0
[   34.813838] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.821797] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.822024] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.822048] adrv9002 spi1.0: Set intf delay clk:6, d:4, tx:1 c:0
[   34.829652] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.837401] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.837626] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.837649] adrv9002 spi1.0: Set intf delay clk:6, d:5, tx:1 c:0
[   34.845091] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.852710] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.852936] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.852959] adrv9002 spi1.0: Set intf delay clk:6, d:6, tx:1 c:0
[   34.860307] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.868005] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.868230] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.868254] adrv9002 spi1.0: Set intf delay clk:6, d:7, tx:1 c:0
[   34.875422] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.883052] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.883279] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.883303] adrv9002 spi1.0: Set intf delay clk:7, d:0, tx:1 c:0
[   34.891169] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.898795] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.899021] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.899045] adrv9002 spi1.0: Set intf delay clk:7, d:1, tx:1 c:0
[   34.906899] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.914414] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.914640] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.914664] adrv9002 spi1.0: Set intf delay clk:7, d:2, tx:1 c:0
[   34.922427] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.930194] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.930423] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.930447] adrv9002 spi1.0: Set intf delay clk:7, d:3, tx:1 c:0
[   34.938211] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.946194] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.946420] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.946444] adrv9002 spi1.0: Set intf delay clk:7, d:4, tx:1 c:0
[   34.953368] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.961170] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.961396] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.961420] adrv9002 spi1.0: Set intf delay clk:7, d:5, tx:1 c:0
[   34.968871] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.976658] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.976885] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.976909] adrv9002 spi1.0: Set intf delay clk:7, d:6, tx:1 c:0
[   34.984231] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   34.991971] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.992196] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   34.992219] adrv9002 spi1.0: Set intf delay clk:7, d:7, tx:1 c:0
[   34.999349] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
[   35.007488] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
[   35.007713] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
[   35.008318] adrv9002 spi1.0: cfg test stop:1, ssi:2, c:0, tx:1
[   35.009333] adrv9002 spi1.0: TX: Got clk: 0, data: 4
[   35.022221] adrv9002 spi1.0: adrv9002-phy Rev 12.0, Firmware 0.22.49,  Stream 0.7.15.0,  API version: 68.16.2 successfully initialized
[   35.026891] cf_axi_adc 84a00000.axi-adrv9002-rx-lpc: ADI AIM (10.03.\x00) probed ADC ADRV9002 as MASTER
[   35.028806] cf_axi_tdd 84a0c800.axi-adrv9002-core-tdd-lpc: Analog Devices CF_AXI_TDD MASTER (1.00.a)
[   35.045182] cf_axi_dds 84a02000.axi-adrv9002-tx-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.02.b) at 0x84A02000 mapped to 0x00000000a46f60d1, probed DDS ADRV9002

I should have verified in the beginning, but as it turns out the carrier has VERY terrible skew and length mismatch between lanes of each channel (upwards of 150ps). The way I understand interface tuning to be implemented, the driver only attempts to correct skew between the clock and ALL the data lanes. So it cannot address skew say between strobe and I or Q.

To fix I tied off the IO Delay Control registers, and instead hard coded delay values directly to compensate for the skew. This means when the driver goes to sweep the delay parameters its not actually changing anything in the PL, all combinations of values it uses should give the same result. Based on the logs this change (combined with flipping polarity in HDL) seems to have got interface tuning to pass.

That LED is still off however, not sure about that one. Will perform more testing and report back.

AubreyTarmu

on Feb 10, 2026 1:23 PM in reply to lf22222
0
Hello,
Sorry for how long it took to get back to you.

okay that's a very a high skew; how many lanes are you using, and what is your sample rate? It seems you've passed SSI tuning, are you able to actually transmit and receive data?

On the LED, not seeing a green isn't the end of the world, however, it would be very bad if you were seeing a red LED, do you see a red LED? Can you probe the 1.8v pins on your carrier
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lf22222
on Feb 10, 2026 5:43 PM in reply to AubreyTarmu
+1
Yeah was able to play and receive tones coherently after correcting the skew with HDL delays.
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suruk
on Mar 11, 2026 7:07 AM in reply to lf22222
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Hi lf22222
We are running into similar issues.
How did you decide what delay values to use? Did you measure it?
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lf22222
on Mar 11, 2026 4:08 PM in reply to suruk
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I used the IDELAYCTRL primitive in the HDL, which lets you specify delay values in picoseconds. This should make selecting delay values pretty intuitive but heres an example:

So lets say all my rx1 traces were 90mm, except for strobe which is 50mm. 40mm difference is ~200-300ps on FR4 (depends on trace type) for example, so just delay strobe by that amount and it will line up. Basically delay the lines so that they match your longest trace.

I didn't measure anything, but I could tell from the driver logs the delays perfectly synchronized the signals.

you can email me if you need more clarification: lei@chiral.systems
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lf22222
on Mar 11, 2026 4:08 PM in reply to suruk
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I used the IDELAYCTRL primitive in the HDL, which lets you specify delay values in picoseconds. This should make selecting delay values pretty intuitive but heres an example:

So lets say all my rx1 traces were 90mm, except for strobe which is 50mm. 40mm difference is ~200-300ps on FR4 (depends on trace type) for example, so just delay strobe by that amount and it will line up. Basically delay the lines so that they match your longest trace.

I didn't measure anything, but I could tell from the driver logs the delays perfectly synchronized the signals.

you can email me if you need more clarification: lei@chiral.systems
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suruk
on Mar 20, 2026 7:17 AM in reply to lf22222
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Thanks for the insight lf22222
Our RX clock is about 40 mm longer than the rest (~300 ps).

So we need to delay all the other data lines by that amount?

Also, doesn't it step through a matrix of delays to find the best combination? From the manual, the step size is about 90 ps. The clock / data delay should have been caught.
(I've posted more details here)

There's other signal polarity concerns as well. We have several I/Q/strobe/clock polarities flipped for RX/TX. There's no clarity if these are being applied correctly either.
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