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Inverted FMC polarity

Thread Summary

The user encountered issues porting the ZCU102 + ADRV9002 reference design to a custom devkit using the TE0701 carrier and TE0820 SOM, due to swapped differential pairs and poor skew/length matching. The solution involved inverting the polarity in HDL using IBUFDS_DIFF_OUT and hard-coding delay values to compensate for the skew, which allowed interface tuning to pass. The user also confirmed that the internal termination circuits in the ADRV9002 do not need to be enabled, as they are already enabled in the FPGA.
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Category: Hardware

Hey all, I'm porting over the ZCU102 + ADRV9002 reference design to a custom devkit (and then down the line to a custom board). I'm using the TE0701 carrier with the TE0820 SOM. The issue is, some of the FMC differential pairs connect to the IOs with swapped polarity. I initially tried  updating the constraints file to reflect how it's physically wired, but Vivado won't let me do that as it actually does check if the physical pin's polarity matches when you use IBUFDS/OBUFDS. So next I tried updating the constraints as if the polarity was correct and just inverting in HDL, but that did not seem to work (interface tuning fails). I also know that the SSI config lets you flip ~some~ signals. But in a previous forumn post it was noted you cant flip RX I/Q individually, only TX. 

The following are flipped on my devkit: fpga_mcs_in, rx1_idata_in, rx1_strobe_in, tx1_dclk_out, tx2_strobe_out. 

What's the correct way to go about porting the reference design in this case? Where should the polarity be corrected?  

  • Hello,

    you are correct you have limited ability to flip the signals in the API, the manual is not ambigious.

    ...


    Let me look into this for you, but a couple of follow up questions first,

    1) What was the original reason that made you want to flip the bits?

    2) Did you correctly terminate the output in your design for the adrv9001 fmc
    3) Can you send me a constraints file & schematic?
    4) How exactly are you inverting the adrv9001 polarity in FPGA? Can you send your model?
    5) Is this test w/ Linux, NO-OS, or TES?

    6) Which HDL are you using for this?
     

  • Thanks for the swift response Aubrey! Here are the details:

    1.) That's just how the off the shelf SOM from Trenz we are using is routed (which I dont have their reason for doing so, but I imagine it made their layout easier). 


    2.) I believe so, I just reused the ZCU102 constraints which has the termination set in the same way. 


    3.) SOM Schematic Carrier Schematic. Attached the constraints at the bottom as well. Since theres 2 schematics it's difficult to map the IO pins to the corresponding FMC pin. I attached the CSV mapping I generated from the carrier netlist for your reference as well. 


    4.) The model is xczu2eg-sfvc784-1-e. In the HDL I invert the polarity in different ways. For RX I made the following changes:
    In `ad_serdes_in` replaced IBUFDS with IBUFDS_DIFF_OUT, then added a vector parameter to specify which lane to flip and which to not. So in my case I can set `RX_INVERT = 'b101`to flip strobe and the I component for RX1. 
    Here is the full git diff:

    diff --git a/library/axi_adrv9001/adrv9001_rx.v b/library/axi_adrv9001/adrv9001_rx.v
    index 5ffffbd17..fc6c06077 100644
    --- a/library/axi_adrv9001/adrv9001_rx.v
    +++ b/library/axi_adrv9001/adrv9001_rx.v
    @@ -40,6 +40,7 @@ module adrv9001_rx #(
       parameter FPGA_TECHNOLOGY = 0,
       parameter EN_RX_MCS_TO_STRB_M = 0,
       parameter NUM_LANES = 3,
    +  parameter [NUM_LANES-1:0] RX_INVERT = {NUM_LANES{1'b0}},
       parameter DRP_WIDTH = 5,
       parameter IODELAY_ENABLE = 1,
       parameter IODELAY_CTRL = 0,
    @@ -129,6 +130,7 @@ module adrv9001_rx #(
         .IODELAY_GROUP (IO_DELAY_GROUP),
         .DDR_OR_SDR_N (DDR_OR_SDR_N),
         .DATA_WIDTH (NUM_LANES),
    +    .RX_INVERT (RX_INVERT),
         .DRP_WIDTH (DRP_WIDTH),
         .SERDES_FACTOR (8)
       ) i_serdes (
    diff --git a/library/axi_adrv9001/axi_adrv9001.v b/library/axi_adrv9001/axi_adrv9001.v
    index fb8d75a21..4bb715c84 100644
    --- a/library/axi_adrv9001/axi_adrv9001.v
    +++ b/library/axi_adrv9001/axi_adrv9001.v
    @@ -46,6 +46,8 @@ module axi_adrv9001 #(
       parameter DISABLE_TX1_SSI = 0,
       parameter DISABLE_RX2_SSI = 0,
       parameter DISABLE_TX2_SSI = 0,
    +  parameter [4:0] RX1_INVERT = 5'b00000,
    +  parameter [4:0] RX2_INVERT = 5'b00000,
       parameter RX_USE_BUFG = 0,
       parameter TX_USE_BUFG = 0,
       parameter IODELAY_CTRL = 1,
    @@ -345,6 +347,8 @@ module axi_adrv9001 #(
         .DISABLE_TX1_SSI (DISABLE_TX1_SSI),
         .DISABLE_RX2_SSI (DISABLE_RX2_SSI),
         .DISABLE_TX2_SSI (DISABLE_TX2_SSI),
    +    .RX1_INVERT (RX1_INVERT[NUM_LANES-1:0]),
    +    .RX2_INVERT (RX2_INVERT[NUM_LANES-1:0]),
         .USE_RX_CLK_FOR_TX1 (USE_RX_CLK_FOR_TX1),
         .USE_RX_CLK_FOR_TX2 (USE_RX_CLK_FOR_TX2)
       ) i_if (
    diff --git a/library/axi_adrv9001/axi_adrv9001_if.v b/library/axi_adrv9001/axi_adrv9001_if.v
    index 5a3fea75f..e3bc48ebb 100644
    --- a/library/axi_adrv9001/axi_adrv9001_if.v
    +++ b/library/axi_adrv9001/axi_adrv9001_if.v
    @@ -47,6 +47,8 @@ module axi_adrv9001_if #(
       parameter DISABLE_TX1_SSI = 0,
       parameter DISABLE_RX2_SSI = 0,
       parameter DISABLE_TX2_SSI = 0,
    +  parameter [NUM_LANES-1:0] RX1_INVERT = {NUM_LANES{1'b0}},
    +  parameter [NUM_LANES-1:0] RX2_INVERT = {NUM_LANES{1'b0}},
       parameter IODELAY_CTRL = 1,
       parameter IODELAY_ENABLE = 1,
       parameter IO_DELAY_GROUP = "dev_if_delay_group",
    @@ -225,6 +227,7 @@ module axi_adrv9001_if #(
           .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
           .EN_RX_MCS_TO_STRB_M (EN_RX_MCS_TO_STRB_M),
           .NUM_LANES (NUM_LANES),
    +      .RX_INVERT (RX1_INVERT),
           .DRP_WIDTH (DRP_WIDTH),
           .IODELAY_CTRL (IODELAY_CTRL),
           .IODELAY_ENABLE (IODELAY_ENABLE),
    @@ -305,6 +308,7 @@ module axi_adrv9001_if #(
           .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
           .EN_RX_MCS_TO_STRB_M (EN_RX_MCS_TO_STRB_M),
           .NUM_LANES (NUM_LANES),
    +      .RX_INVERT (RX2_INVERT),
           .DRP_WIDTH (DRP_WIDTH),
           .IODELAY_CTRL (DISABLE_RX1_SSI),
           .IODELAY_ENABLE (IODELAY_ENABLE),
    diff --git a/library/xilinx/common/ad_serdes_in.v b/library/xilinx/common/ad_serdes_in.v
    index acbb1c0a8..04635f55e 100644
    --- a/library/xilinx/common/ad_serdes_in.v
    +++ b/library/xilinx/common/ad_serdes_in.v
    @@ -42,6 +42,7 @@ module ad_serdes_in #(
       parameter   DDR_OR_SDR_N = 0,
       parameter   SERDES_FACTOR = 8,
       parameter   DATA_WIDTH = 16,
    +  parameter   [DATA_WIDTH-1:0] RX_INVERT = {DATA_WIDTH{1'b0}},
       parameter   DRP_WIDTH = 5,
       parameter   IODELAY_ENABLE = 1,
       parameter   IODELAY_CTRL = 0,
    @@ -107,6 +108,8 @@ module ad_serdes_in #(
       // internal signals
     
       wire  [(DATA_WIDTH-1):0]      data_in_ibuf_s;
    +  wire  [(DATA_WIDTH-1):0]      data_in_ibuf_o;
    +  wire  [(DATA_WIDTH-1):0]      data_in_ibuf_ob;
       wire  [(DATA_WIDTH-1):0]      data_in_idelay_s;
       wire  [(DATA_WIDTH-1):0]      data_shift1_s;
       wire  [(DATA_WIDTH-1):0]      data_shift2_s;
    @@ -137,10 +140,17 @@ module ad_serdes_in #(
       generate
       for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_io
         if (CMOS_LVDS_N == 0) begin
    -      IBUFDS i_ibuf (
    +      IBUFDS_DIFF_OUT i_ibuf (
             .I (data_in_p[l_inst]),
             .IB (data_in_n[l_inst]),
    -        .O (data_in_ibuf_s[l_inst]));
    +        .O (data_in_ibuf_o[l_inst]),
    +        .OB (data_in_ibuf_ob[l_inst]));
    +
    +      if (RX_INVERT[l_inst] == 1'b1) begin : g_inv
    +        assign data_in_ibuf_s[l_inst] = data_in_ibuf_ob[l_inst];
    +      end else begin : g_noinv
    +        assign data_in_ibuf_s[l_inst] = data_in_ibuf_o[l_inst];
    +      end
         end else begin
           IBUF i_ibuf (
             .I (data_in_p[l_inst]),
    

    For mcs I just flip directly like so in system_top.v:
      IBUFDS i_ibufgs_fpga_mcs_in (
        .I (fpga_mcs_in_p),
        .IB (fpga_mcs_in_n),
        .O (fpga_mcs_in_raw));
    
      assign fpga_mcs_in = ~fpga_mcs_in_raw;
    

    For TX it uses the RX SSI clock so I'm not sure it matters that tx1_dclk_out is flipped? For tx2_strobe_out I flipped in the SSI config by setting `lvdsStrobeBitInversion` to true in the LVDS json config. Based on the linux logs though, we fail RX1 interface tuning before we get to TX. 

    Do let me know if this is not ideal and theres a better way of doing this!

    5.) Linux with the standard driver:

    Dec 20 01:28:18 zcu102 kernel: axi_sysid 85000000.axi-sysid-0: [adrv9001] [LVDS] on [trenz] git branch <main> git <c23b17c33112b0c3f31e2f48ad0e654677993771> dirty [2026-01-17 20:01:47] UTC
    Dec 20 01:28:38 zcu102 kernel: platform 84a00000.axi-adrv9002-rx-lpc: deferred probe pending: (reason unknown)
    Dec 20 01:28:38 zcu102 kernel: platform 84a0c800.axi-adrv9002-core-tdd-lpc: deferred probe pending: (reason unknown)
    Dec 20 01:28:38 zcu102 kernel: platform 84a02000.axi-adrv9002-tx-lpc: deferred probe pending: (reason unknown)
    Dec 20 01:28:44 zcu102 kernel: adrv9002 spi1.0: Tx1 SSI clk driven by RX1 REF
    Dec 20 01:28:44 zcu102 kernel: adrv9002 spi1.0: Tx2 SSI clk driven by RX2 REF
    Dec 20 01:28:44 zcu102 kernel: adrv9002 spi1.0: RX1 enabled
    Dec 20 01:28:44 zcu102 kernel: adrv9002 spi1.0: RX2 enabled
    Dec 20 01:28:44 zcu102 kernel: adrv9002 spi1.0: TX1 enabled
    Dec 20 01:28:44 zcu102 kernel: adrv9002 spi1.0: TX2 enabled
    Dec 20 01:28:44 zcu102 kernel: adrv9002 spi1.0: pos: 15, Chan1:1BE5F7, Chan2:1BE5F7
    Dec 20 01:28:47 zcu102 kernel: adrv9002 spi1.0: Requesting warmboot coefficients: "Navassa_LVDS_init_cals.bin"n
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set dpgio: 2, signal: 1
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set dpgio: 1, signal: 0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 30720000 Hz
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 30720000 Hz
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:0, d:0, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:0, d:1, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:0, d:2, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:0, d:3, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:0, d:4, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:0, d:5, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:0, d:6, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:0, d:7, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:1, d:0, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:1, d:1, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:1, d:2, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:1, d:3, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:1, d:4, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:1, d:5, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:1, d:6, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:1, d:7, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:2, d:0, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:2, d:1, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:2, d:2, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:2, d:3, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:2, d:4, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:2, d:5, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:2, d:6, tx:0 c:0
    Dec 20 01:28:48 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:2, d:7, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:3, d:0, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:3, d:1, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:3, d:2, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:3, d:3, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:3, d:4, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:3, d:5, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:3, d:6, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:3, d:7, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:4, d:0, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:4, d:1, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:4, d:2, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:4, d:3, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:4, d:4, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:4, d:5, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:4, d:6, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:4, d:7, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:5, d:0, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:5, d:1, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:5, d:2, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:5, d:3, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:5, d:4, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:5, d:5, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:5, d:6, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:5, d:7, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:6, d:0, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:6, d:1, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:6, d:2, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:6, d:3, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:6, d:4, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:6, d:5, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:6, d:6, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:6, d:7, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:7, d:0, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:7, d:1, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:7, d:2, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:7, d:3, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:7, d:4, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:7, d:5, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:7, d:6, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Set intf delay clk:7, d:7, tx:0 c:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: pn error in c:0, reg: 02
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: cfg test stop:1, ssi:2, c:0, tx:0
    Dec 20 01:28:49 zcu102 kernel: adrv9002 spi1.0: Interface tuning failed: -5
    Dec 20 01:28:49 zcu102 kernel: cf_axi_adc 84a00000.axi-adrv9002-rx-lpc: probe with driver cf_axi_adc failed with error -5

    6.) Standard ADI hdl repo. I just ported the zcu102 block design to the 2eg. 

    ###############################################################################
    ## Copyright (C) 2020-2023, 2025 Analog Devices, Inc. All rights reserved.
    ### SPDX short identifier: ADIBSD
    ###############################################################################
    
    set_property  -dict {PACKAGE_PIN C2     IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx1_dclk_in_n]     ;## FMC_HPC0_LA00_CC_N IO_L13N_T2L_N1_GC_QBC_66
    set_property  -dict {PACKAGE_PIN C3     IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx1_dclk_in_p]     ;## FMC_HPC0_LA00_CC_P IO_L13P_T2L_N0_GC_QBC_66
    ## The below 2 pins are swapped
    set_property  -dict {PACKAGE_PIN F1     IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx1_idata_in_n]    ;## FMC_HPC0_LA03_N    IO_L22N_T3U_N7_DBC_AD0N_66
    set_property  -dict {PACKAGE_PIN G1     IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx1_idata_in_p]    ;## FMC_HPC0_LA03_P    IO_L22P_T3U_N6_DBC_AD0P_66
    set_property  -dict {PACKAGE_PIN D1     IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx1_qdata_in_n]    ;## FMC_HPC0_LA04_N    IO_L21N_T3L_N5_AD8N_66
    set_property  -dict {PACKAGE_PIN E1     IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx1_qdata_in_p]    ;## FMC_HPC0_LA04_P    IO_L21P_T3L_N4_AD8P_66
    ## The below 2 pins are swapped
    set_property  -dict {PACKAGE_PIN A1     IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx1_strobe_in_n]   ;## FMC_HPC0_LA02_N    IO_L23N_T3U_N9_66
    set_property  -dict {PACKAGE_PIN A2     IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx1_strobe_in_p]   ;## FMC_HPC0_LA02_P    IO_L23P_T3U_N8_66
    
    set_property  -dict {PACKAGE_PIN AD4    IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx2_dclk_in_n]     ;## FMC_HPC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67
    set_property  -dict {PACKAGE_PIN AD5    IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx2_dclk_in_p]     ;## FMC_HPC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67
    set_property  -dict {PACKAGE_PIN AC2    IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx2_idata_in_n]    ;## FMC_HPC0_LA20_N    IO_L22N_T3U_N7_DBC_AD0N_67
    set_property  -dict {PACKAGE_PIN AB2    IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx2_idata_in_p]    ;## FMC_HPC0_LA20_P    IO_L22P_T3U_N6_DBC_AD0P_67
    set_property  -dict {PACKAGE_PIN AD1    IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx2_qdata_in_n]    ;## FMC_HPC0_LA19_N    IO_L23N_T3U_N9_67
    set_property  -dict {PACKAGE_PIN AD2    IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx2_qdata_in_p]    ;## FMC_HPC0_LA19_P    IO_L23P_T3U_N8_67
    set_property  -dict {PACKAGE_PIN AH4    IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx2_strobe_in_n]   ;## FMC_HPC0_LA21_N    IO_L21N_T3L_N5_AD8N_67
    set_property  -dict {PACKAGE_PIN AG4    IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports rx2_strobe_in_p]   ;## FMC_HPC0_LA21_P    IO_L21P_T3L_N4_AD8P_67
    
    ## The below 2 pins are swapped
    set_property  -dict {PACKAGE_PIN A6     IOSTANDARD LVDS}                          [get_ports tx1_dclk_out_n]    ;## FMC_HPC0_LA07_N    IO_L18N_T2U_N11_AD2N_66
    set_property  -dict {PACKAGE_PIN A7     IOSTANDARD LVDS}                          [get_ports tx1_dclk_out_p]    ;## FMC_HPC0_LA07_P    IO_L18P_T2U_N10_AD2P_66
    set_property  -dict {PACKAGE_PIN C4     IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports tx1_dclk_in_n]     ;## FMC_HPC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66
    set_property  -dict {PACKAGE_PIN D4     IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports tx1_dclk_in_p]     ;## FMC_HPC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66
    set_property  -dict {PACKAGE_PIN A4     IOSTANDARD LVDS}                          [get_ports tx1_idata_out_n]   ;## FMC_HPC0_LA08_N    IO_L17N_T2U_N9_AD10N_66
    set_property  -dict {PACKAGE_PIN B4     IOSTANDARD LVDS}                          [get_ports tx1_idata_out_p]   ;## FMC_HPC0_LA08_P    IO_L17P_T2U_N8_AD10P_66
    set_property  -dict {PACKAGE_PIN B6     IOSTANDARD LVDS}                          [get_ports tx1_qdata_out_n]   ;## FMC_HPC0_LA05_N    IO_L20N_T3L_N3_AD1N_66
    set_property  -dict {PACKAGE_PIN C6     IOSTANDARD LVDS}                          [get_ports tx1_qdata_out_p]   ;## FMC_HPC0_LA05_P    IO_L20P_T3L_N2_AD1P_66
    set_property  -dict {PACKAGE_PIN B1     IOSTANDARD LVDS}                          [get_ports tx1_strobe_out_n]  ;## FMC_HPC0_LA06_N    IO_L19N_T3L_N1_DBC_AD9N_66
    set_property  -dict {PACKAGE_PIN C1     IOSTANDARD LVDS}                          [get_ports tx1_strobe_out_p]  ;## FMC_HPC0_LA06_P    IO_L19P_T3L_N0_DBC_AD9P_66
    
    set_property  -dict {PACKAGE_PIN AF3    IOSTANDARD LVDS}                          [get_ports tx2_dclk_out_n]    ;## FMC_HPC0_LA22_N    IO_L20N_T3L_N3_AD1N_67
    set_property  -dict {PACKAGE_PIN AE3    IOSTANDARD LVDS}                          [get_ports tx2_dclk_out_p]    ;## FMC_HPC0_LA22_P    IO_L20P_T3L_N2_AD1P_67
    set_property  -dict {PACKAGE_PIN AC3    IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports tx2_dclk_in_n]     ;## FMC_HPC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67
    set_property  -dict {PACKAGE_PIN AC4    IOSTANDARD LVDS  DIFF_TERM_ADV TERM_100}  [get_ports tx2_dclk_in_p]     ;## FMC_HPC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67
    set_property  -dict {PACKAGE_PIN AC1    IOSTANDARD LVDS}                          [get_ports tx2_idata_out_n]   ;## FMC_HPC0_LA23_N    IO_L19N_T3L_N1_DBC_AD9N_67
    set_property  -dict {PACKAGE_PIN AB1    IOSTANDARD LVDS}                          [get_ports tx2_idata_out_p]   ;## FMC_HPC0_LA23_P    IO_L19P_T3L_N0_DBC_AD9P_67
    set_property  -dict {PACKAGE_PIN AH3    IOSTANDARD LVDS}                          [get_ports tx2_qdata_out_n]   ;## FMC_HPC0_LA25_N    IO_L17N_T2U_N9_AD10N_67
    set_property  -dict {PACKAGE_PIN AG3    IOSTANDARD LVDS}                          [get_ports tx2_qdata_out_p]   ;## FMC_HPC0_LA25_P    IO_L17P_T2U_N8_AD10P_67
    ## The below 2 pins are swapped
    set_property  -dict {PACKAGE_PIN AH1    IOSTANDARD LVDS}                          [get_ports tx2_strobe_out_n]  ;## FMC_HPC0_LA24_N    IO_L18N_T2U_N11_AD2N_67
    set_property  -dict {PACKAGE_PIN AH2    IOSTANDARD LVDS}                          [get_ports tx2_strobe_out_p]  ;## FMC_HPC0_LA24_P    IO_L18P_T2U_N10_AD2P_67
    
    # clocks
    
    create_clock -name ref_clk        -period  8.00 [get_ports fpga_ref_clk_p]
    
    create_clock -name rx1_dclk_out   -period  2.0  -waveform {0.0 1.0} [get_ports rx1_dclk_in_p]
    create_clock -name rx2_dclk_out   -period  2.0  -waveform {0.0 1.0} [get_ports rx2_dclk_in_p]
    create_clock -name tx1_dclk_out   -period  2.0  -waveform {0.0 1.0} [get_ports tx1_dclk_in_p]
    create_clock -name tx2_dclk_out   -period  2.0  -waveform {0.0 1.0} [get_ports tx2_dclk_in_p]
    
    # Allow max skew of 0.2 ns between input clocks
    set_clock_latency -source -early -0.1 [get_clocks rx1_dclk_out]
    set_clock_latency -source -early -0.1 [get_clocks rx2_dclk_out]
    
    set_clock_latency -source -late 0.1 [get_clocks rx1_dclk_out]
    set_clock_latency -source -late 0.1 [get_clocks rx2_dclk_out]
    
    set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS_1 \
      [list [get_nets -of [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O]] \
            [get_nets -of [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_buf_fast/O]] \
      ]
    
    set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS_2 \
      [list [get_nets -of [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O]] \
            [get_nets -of [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_buf_fast/O]] \
      ]
    
    set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS_3 \
      [list [get_nets -of [get_pins {i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_div_clk_buf/O}]] \
            [get_nets -of [get_pins {i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_1_phy/i_clk_buf_fast/O}]] \
      ]
    
    set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS_4 \
      [list [get_nets -of [get_pins {i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_div_clk_buf/O}]] \
            [get_nets -of [get_pins {i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_tx_2_phy/i_clk_buf_fast/O}]] \
      ]
    
    set_input_delay -clock [get_clocks {ref_clk}] -min -add_delay 2.0 [get_ports {fpga_mcs_in_p}]
    set_input_delay -clock [get_clocks {ref_clk}] -max -add_delay 3.0 [get_ports {fpga_mcs_in_p}]
    
    set_false_path -to [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_sync/mssi_sync_in_d_reg/D]
    
    ###############################################################################
    ## Copyright (C) 2020-2023, 2025 Analog Devices, Inc. All rights reserved.
    ### SPDX short identifier: ADIBSD
    ###############################################################################
    
    set_property  -dict {PACKAGE_PIN E5    IOSTANDARD LVCMOS18}  [get_ports dev_clk_in]                        ; #FMC_HPC0_CLK0_M2C_P  
    set_property  -dict {PACKAGE_PIN E8    IOSTANDARD LVDS}      [get_ports dev_mcs_fpga_out_n]                ; #FMC_HPC0_LA14_N      
    set_property  -dict {PACKAGE_PIN F8    IOSTANDARD LVDS}      [get_ports dev_mcs_fpga_out_p]                ; #FMC_HPC0_LA14_P      
    
    set_property  -dict {PACKAGE_PIN F7    IOSTANDARD LVCMOS18}  [get_ports dgpio_0]                           ; #FMC_HPC0_LA16_P      
    set_property  -dict {PACKAGE_PIN G8    IOSTANDARD LVCMOS18}  [get_ports dgpio_1]                           ; #FMC_HPC0_LA16_N      
    set_property  -dict {PACKAGE_PIN E9    IOSTANDARD LVCMOS18}  [get_ports dgpio_2]                           ; #FMC_HPC0_LA15_N      
    set_property  -dict {PACKAGE_PIN F2    IOSTANDARD LVCMOS18}  [get_ports dgpio_3]                           ; #FMC_HPC0_LA11_N      
    set_property  -dict {PACKAGE_PIN A8    IOSTANDARD LVCMOS18}  [get_ports dgpio_4]                           ; #FMC_HPC0_LA09_N      
    set_property  -dict {PACKAGE_PIN C9    IOSTANDARD LVCMOS18}  [get_ports dgpio_5]                           ; #FMC_HPC0_LA10_N      
    set_property  -dict {PACKAGE_PIN AE2   IOSTANDARD LVCMOS18}  [get_ports dgpio_6]                           ; #FMC_HPC0_LA27_P      
    set_property  -dict {PACKAGE_PIN AG6   IOSTANDARD LVCMOS18}  [get_ports dgpio_7]                           ; #FMC_HPC0_LA26_P      
    set_property  -dict {PACKAGE_PIN AC7   IOSTANDARD LVCMOS18}  [get_ports dgpio_8]                           ; #FMC_HPC0_LA28_P      
    set_property  -dict {PACKAGE_PIN AB7   IOSTANDARD LVCMOS18}  [get_ports dgpio_9]                           ; #FMC_HPC0_LA28_N      
    set_property  -dict {PACKAGE_PIN E2    IOSTANDARD LVCMOS18}  [get_ports dgpio_10]                          ; #FMC_HPC0_LA11_P      
    set_property  -dict {PACKAGE_PIN AF2   IOSTANDARD LVCMOS18}  [get_ports dgpio_11]                          ; #FMC_HPC0_LA27_N      
    
    ## NOTE: Board-level P/N swap for fpga_mcs_in; HDL inverts after IBUFDS.
    set_property  -dict {PACKAGE_PIN AG9   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100}  [get_ports fpga_mcs_in_n]  ; #FMC_HPC0_LA32_N      
    set_property  -dict {PACKAGE_PIN AH9   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100}  [get_ports fpga_mcs_in_p]  ; #FMC_HPC0_LA32_P      
    set_property  -dict {PACKAGE_PIN D6    IOSTANDARD LVDS DIFF_TERM_ADV TERM_100}  [get_ports fpga_ref_clk_n] ; #FMC_HPC0_CLK1_M2C_N  
    set_property  -dict {PACKAGE_PIN D7    IOSTANDARD LVDS DIFF_TERM_ADV TERM_100}  [get_ports fpga_ref_clk_p] ; #FMC_HPC0_CLK1_M2C_P  
    set_property  -dict {PACKAGE_PIN AH8   IOSTANDARD LVCMOS18}  [get_ports gp_int]                            ; #FMC_HPC0_LA30_P      
    set_property  -dict {PACKAGE_PIN F6    IOSTANDARD LVCMOS18}  [get_ports mode]                              ; #FMC_HPC0_LA13_P      
    set_property  -dict {PACKAGE_PIN G6    IOSTANDARD LVCMOS18}  [get_ports reset_trx]                         ; #FMC_HPC0_LA13_N      
    
    set_property  -dict {PACKAGE_PIN B9    IOSTANDARD LVCMOS18}  [get_ports rx1_enable]                        ; #FMC_HPC0_LA10_P      
    set_property  -dict {PACKAGE_PIN AG5   IOSTANDARD LVCMOS18}  [get_ports rx2_enable]                        ; #FMC_HPC0_LA26_N      
    
    set_property  -dict {PACKAGE_PIN D5    IOSTANDARD LVCMOS18}  [get_ports sm_fan_tach]                       ; #FMC_HPC0_CLK0_M2C_N  
    
    set_property  -dict {PACKAGE_PIN E3    IOSTANDARD LVCMOS18}  [get_ports spi_clk]                           ; #FMC_HPC0_LA12_P      
    set_property  -dict {PACKAGE_PIN AB6   IOSTANDARD LVCMOS18}  [get_ports spi_dio]                           ; #FMC_HPC0_LA29_N      
    set_property  -dict {PACKAGE_PIN E4    IOSTANDARD LVCMOS18}  [get_ports spi_do]                            ; #FMC_HPC0_LA12_N      
    set_property  -dict {PACKAGE_PIN D9    IOSTANDARD LVCMOS18}  [get_ports spi_en]                            ; #FMC_HPC0_LA15_P      
    
    set_property  -dict {PACKAGE_PIN A9    IOSTANDARD LVCMOS18}  [get_ports tx1_enable]                        ; #FMC_HPC0_LA09_P      
    set_property  -dict {PACKAGE_PIN AC6   IOSTANDARD LVCMOS18}  [get_ports tx2_enable]                        ; #FMC_HPC0_LA29_P      
    
    set_property  -dict {PACKAGE_PIN AE7    IOSTANDARD LVCMOS18}  [get_ports vadj_err]                          ; #FMC_HPC0_LA31_P      
    set_property  -dict {PACKAGE_PIN AD7    IOSTANDARD LVCMOS18}  [get_ports platform_status]                   ; #FMC_HPC0_LA31_N      
    
    set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx1_strobe_out_p]
    set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx1_strobe_out_n]
    
    set_property PACKAGE_PIN H1 [get_ports IIC_CPLD_scl_io]
    set_property PACKAGE_PIN J1 [get_ports IIC_CPLD_sda_io]
    set_property IOSTANDARD LVCMOS18 [get_ports IIC_CPLD_scl_io]
    set_property IOSTANDARD LVCMOS18 [get_ports IIC_CPLD_sda_io]
    set_property PULLTYPE PULLUP [get_ports [list IIC_CPLD_scl_io]]
    set_property PULLTYPE PULLUP [get_ports [list IIC_CPLD_sda_io]]
    
    ,,,,,
    ADI Pin,FMC Signal,JB Connector,JB Pin,IO Pin Name,IO Pin
    DGPIO_2,FMC_LA15_N,JB1,35,B66_L18_P,E9
    SPI_EN,FMC_LA15_P,JB1,37,B66_L18_N,D9
    DGPIO_1,FMC_LA16_N,JB1,39,B66_L16_P,G8
    DGPIO_0,FMC_LA16_P,JB1,41,B66_L16_N,F7
    DEV_MCS_FPGA_IN-,FMC_LA14_N,JB1,45,B66_L17_N,E8
    TX1_QDATA_IN-,FMC_LA5_N,JB1,46,B66_L20_N,B6
    DEV_MCS_FPGA_IN+,FMC_LA14_P,JB1,47,B66_L17_P,F8
    TX1_QDATA_IN+,FMC_LA5_P,JB1,48,B66_L20_P,C6
    RESET,FMC_LA13_N,JB1,49,B66_L15_P,G6
    TX1_STROBE_IN-,FMC_LA6_N,JB1,50,B66_L7_N,B1
    MODE,FMC_LA13_P,JB1,51,B66_L15_N,F6
    TX1_STROBE_IN+,FMC_LA6_P,JB1,52,B66_L7_P,C1
    DGPIO_3,FMC_LA11_N,JB1,55,B66_L3_P,F2
    RX1_QDATA_OUT-,FMC_LA4_N,JB1,56,B66_L2_N,D1
    DGPIO_10,FMC_LA11_P,JB1,57,B66_L3_N,E2
    RX1_QDATA_OUT+,FMC_LA4_P,JB1,58,B66_L2_P,E1
    SPI_DO,FMC_LA12_N,JB1,59,B66_L5_P,E4
    ,FMC_CLK0_N,JB1,60,B66_L14_N,D5
    SPI_CLK,FMC_LA12_P,JB1,61,B66_L5_N,E3
    DEV_CLK_OUT,FMC_CLK0_P,JB1,62,B66_L14_P,E5
    FPGA_REF_CLK-,FMC_CLK1_N,JB1,65,B66_L13_N,D6
    DGPIO_12/TX1_DCLK_OUT-,FMC_LA1_N,JB1,66,B66_L11_N,C4
    FPGA_REF_CLK+,FMC_CLK1_P,JB1,67,B66_L13_P,D7
    DGPIO_12/TX1_DCLK_OUT+,FMC_LA1_P,JB1,68,B66_L11_P,D4
    DGPIO_5,FMC_LA10_N,JB1,69,B66_L24_P,C9
    RX1_IDATA_OUT-,FMC_LA3_N,JB1,70,B66_L1_P,G1
    RX1_ENABLE,FMC_LA10_P,JB1,71,B66_L24_N,B9
    RX1_IDATA_OUT+,FMC_LA3_P,JB1,72,B66_L1_N,F1
    DGPIO_4,FMC_LA9_N,JB1,75,B66_L23_N,A8
    RX1_DCLK_OUT-,FMC_LA0_N,JB1,76,B66_L12_N,C2
    TX1_ENABLE,FMC_LA9_P,JB1,77,B66_L23_P,A9
    RX1_DCLK_OUT+,FMC_LA0_P,JB1,78,B66_L12_P,C3
    TX1_DCLK_IN-,FMC_LA7_N,JB1,79,B66_L21_P,A7
    TX1_DCLK_IN+,FMC_LA7_P,JB1,81,B66_L21_N,A6
    RX1_STROBE_OUT-,FMC_LA2_N,JB1,82,B66_L8_P,A2
    RX1_STROBE_OUT+,FMC_LA2_P,JB1,84,B66_L8_N,A1
    ,FMC_VREF,JB1,85,,
    TX1_IDATA_IN-,FMC_LA8_N,JB1,93,B66_L10_N,A4
    TX1_IDATA_IN+,FMC_LA8_P,JB1,95,B66_L10_P,B4
    ,FMC_VREF,JB1,97,,
    ,FMC_VREF,JB2,37,,
    RX2_IDATA_OUT+,FMC_LA20_P,JB2,46,B64_L17_P,AB2
    RX2_IDATA_OUT-,FMC_LA20_N,JB2,48,B64_L17_N,AC2
    DGPIO_15/TX2_DCLK_OUT+,FMC_LA18_P,JB2,52,B64_L14_P,AC4
    DGPIO_14/TX2_DCLK_OUT-,FMC_LA18_N,JB2,54,B64_L14_N,AC3
    RX2_DCLK_OUT+,FMC_LA17_P,JB2,55,B64_L13_P,AD5
    TX2_IDATA_IN+,FMC_LA23_P,JB2,56,B64_L18_P,AB1
    RX2_DCLK_OUT-,FMC_LA17_N,JB2,57,B64_L13_N,AD4
    TX2_IDATA_IN-,FMC_LA23_N,JB2,58,B64_L18_N,AC1
    FPGA_MCS_IN-,FMC_LA32_N,JB2,61,B64_L7_P,AG9
    RX2_QDATA_OUT+,FMC_LA19_P,JB2,62,B64_L16_P,AD2
    FPGA_MCS_IN+,FMC_LA32_P,JB2,63,B64_L7_N,AH9
    RX2_QDATA_OUT-,FMC_LA19_N,JB2,64,B64_L16_N,AD1
    ,FMC_LA33_N,JB2,65,,
    TX2_DCLK_IN+,FMC_LA22_P,JB2,66,B64_L21_P,AE3
    ,FMC_LA33_P,JB2,67,,
    TX2_DCLK_IN-,FMC_LA22_N,JB2,68,B64_L21_N,AF3
    ,FMC_LA30_N,JB2,71,,
    DGPIO_6,FMC_LA27_P,JB2,72,B64_L22_P,AE2
    GP_INT,FMC_LA30_P,JB2,73,B64_L9_P,AH8
    DGPIO_11,FMC_LA27_N,JB2,74,B64_L22_N,AF2
    ,FMC_LA31_N,JB2,75,,
    DGPIO_7,FMC_LA26_P,JB2,76,B64_L10_P,AG6
    ,FMC_LA31_P,JB2,77,,
    RX2_ENABLE,FMC_LA26_N,JB2,78,B64_L10_N,AG5
    DGPIO_9,FMC_LA28_N,JB2,81,B64_L5_P,AB7
    RX2_STROBE_OUT+,FMC_LA21_P,JB2,82,B64_L19_P,AG4
    DGPIO_8,FMC_LA28_P,JB2,83,B64_L5_N,AC7
    RX2_STROBE_OUT-,FMC_LA21_N,JB2,84,B64_L19_N,AH4
    SPI_DIO,FMC_LA29_N,JB2,85,B64_L6_P,AB6
    TX2_QDATA_IN+,FMC_LA25_P,JB2,86,B64_L20_P,AG3
    TX2_ENABLE,FMC_LA29_P,JB2,87,B64_L6_N,AC6
    TX2_QDATA_IN-,FMC_LA25_N,JB2,88,B64_L20_N,AH3
    ,FMC_VREF,JB2,93,,
    TX2_STROBE_IN-,FMC_LA24_N,JB2,95,B64_L23_P,AH2
    TX2_STROBE_IN+,FMC_LA24_P,JB2,97,B64_L23_N,AH1

    Sorry if this is kind of confusing. Let me know if I can elaborate on anything or provide more details. And thanks for taking a look!

  • Just following up, I found the official pinout for the Trenz board. 
    PDF

  • Hello,
    1) to clarify when you say the below two are swapped you don't mean you are using a separate constraints file than what you just shared where you have those pins actually swapped? This is your current active constraints correct?
    2) A lot of the issues we see with interface tuning is related to improper termination (either adding an extra 100 ohm resistor, or not adding one at all). I looked at your schematic, for A1/A2 looking for an extra resistor but the link you sent me keeps crashing now, so I would recommend looking at the schematic again to see if they added an extra resistor.
    3) I'm very confused why you decided to flip it in both the HDL & in the json kernel settings can you elaborate on that decision? It seems you should be able to get away with just flipping the input and outputs in the HDL, but I see you have done quite a bit of logic in your HDL, do you mind explaining if your HDL changes are there to do more than just invert?

    Best, Aubrey

  • 1.) Yeah thats the active constraints file, theres no separate one. So for example, in the pcb its routed rx1_idata_in_n -> G1, rx1_idata_in_n -> F1. It's flipped in the constraints file so Vivado doesn't complain. 

    2.) Yeah double checked the schematics, neither the som nor the carrier has physical termination. The FMC directly connects to the IO banks through the B2B connectors. Is there any configuration needed to enable the internal termination circuits in the ADRV? Already have them enabled in the FPGA. 

    3.) I'll try again but do it all in HDL. The reason I mixed and matched is because the tx ones were easier to do in json, guess thats over complicated. Yeah all my change does is invert, it's just a lot of boilerplate because I made it a top level parameter I can configure in Vivado GUI. 



    I additionally wanted to ask what the significance of the bottom left LED is. I notice on the ZCU102 it's green (the smaller left one). Maybe this is a clue?

  • Hello, 

     Is there any configuration needed to enable the internal termination circuits in the ADRV? Already have them enabled in the FPGA.

    No

    what the significance of the bottom left LED is.

    It means you're failing vadj_test, you need to have the voltage at 1.8v. Do you have it set to 1.8v? The part will not work without that LED on.

  • Hey Aubrey, I do have 1.8v, it's set via a dip switch. When I use a barebones vivado design (no adrv and no fmc configuration), just the zynqmp block, the LED is in fact on. But it's off when using my modified design for the adrv9001. Should be noted that I'm not an FPGA engineer, but is there anything constraints wise that could cause this? The vadj setting should be external to the fpga on this devkit. 

    Thanks!

  • I believe I have fixed the issue? Do these logs indicate it's operating nominally:

    [    1.856409] axi_sysid 85000000.axi-sysid-0: [adrv9001] [LVDS] on [trenz] git branch <main> git <c23b17c33112b0c3f31e2f48ad0e654677993771> dirty [2026-01-27 00:31:20] UTC
    [   17.121915] platform 84a00000.axi-adrv9002-rx-lpc: deferred probe pending: (reason unknown)
    [   17.121948] platform 84a0c800.axi-adrv9002-core-tdd-lpc: deferred probe pending: (reason unknown)
    [   17.121963] platform 84a02000.axi-adrv9002-tx-lpc: deferred probe pending: (reason unknown)
    [   28.478717] adrv9002 spi1.0: Tx1 SSI clk driven by RX1 REF
    [   28.478755] adrv9002 spi1.0: Tx2 SSI clk driven by RX2 REF
    [   28.497431] adrv9002 spi1.0: RX1 enabled
    [   28.497470] adrv9002 spi1.0: RX2 enabled
    [   28.497486] adrv9002 spi1.0: TX1 enabled
    [   28.497502] adrv9002 spi1.0: TX2 enabled
    [   28.497518] adrv9002 spi1.0: pos: 15, Chan1:1BE5F7, Chan2:1BE5F7
    [   32.018014] adrv9002 spi1.0: Requesting warmboot coefficients: "Navassa_LVDS_init_cals.bin"n
    [   33.170848] adrv9002 spi1.0: Set dpgio: 2, signal: 1
    [   33.171283] adrv9002 spi1.0: Set dpgio: 1, signal: 0
    [   33.171704] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
    [   33.171727] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
    [   33.171749] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
    [   33.171766] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
    [   33.171785] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
    [   33.171843] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 15360000 Hz
    [   33.182168] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 30720000 Hz
    [   33.182193] adrv9002 spi1.0: adrv9002_bb_round_rate: Rate 30720000 Hz
    [   33.182217] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:0
    [   33.183579] adrv9002 spi1.0: Set intf delay clk:0, d:0, tx:0 c:0
    [   33.191162] adrv9002 spi1.0: Set intf delay clk:0, d:1, tx:0 c:0
    [   33.198581] adrv9002 spi1.0: Set intf delay clk:0, d:2, tx:0 c:0
    [   33.206015] adrv9002 spi1.0: Set intf delay clk:0, d:3, tx:0 c:0
    [   33.212863] adrv9002 spi1.0: Set intf delay clk:0, d:4, tx:0 c:0
    [   33.220257] adrv9002 spi1.0: Set intf delay clk:0, d:5, tx:0 c:0
    [   33.227659] adrv9002 spi1.0: Set intf delay clk:0, d:6, tx:0 c:0
    [   33.235123] adrv9002 spi1.0: Set intf delay clk:0, d:7, tx:0 c:0
    [   33.242584] adrv9002 spi1.0: Set intf delay clk:1, d:0, tx:0 c:0
    [   33.250054] adrv9002 spi1.0: Set intf delay clk:1, d:1, tx:0 c:0
    [   33.258300] adrv9002 spi1.0: Set intf delay clk:1, d:2, tx:0 c:0
    [   33.266504] adrv9002 spi1.0: Set intf delay clk:1, d:3, tx:0 c:0
    [   33.274632] adrv9002 spi1.0: Set intf delay clk:1, d:4, tx:0 c:0
    [   33.282794] adrv9002 spi1.0: Set intf delay clk:1, d:5, tx:0 c:0
    [   33.290994] adrv9002 spi1.0: Set intf delay clk:1, d:6, tx:0 c:0
    [   33.299321] adrv9002 spi1.0: Set intf delay clk:1, d:7, tx:0 c:0
    [   33.309329] adrv9002 spi1.0: Set intf delay clk:2, d:0, tx:0 c:0
    [   33.318835] adrv9002 spi1.0: Set intf delay clk:2, d:1, tx:0 c:0
    [   33.328198] adrv9002 spi1.0: Set intf delay clk:2, d:2, tx:0 c:0
    [   33.337440] adrv9002 spi1.0: Set intf delay clk:2, d:3, tx:0 c:0
    [   33.347178] adrv9002 spi1.0: Set intf delay clk:2, d:4, tx:0 c:0
    [   33.357575] adrv9002 spi1.0: Set intf delay clk:2, d:5, tx:0 c:0
    [   33.367337] adrv9002 spi1.0: Set intf delay clk:2, d:6, tx:0 c:0
    [   33.377578] adrv9002 spi1.0: Set intf delay clk:2, d:7, tx:0 c:0
    [   33.387776] adrv9002 spi1.0: Set intf delay clk:3, d:0, tx:0 c:0
    [   33.397147] adrv9002 spi1.0: Set intf delay clk:3, d:1, tx:0 c:0
    [   33.406779] adrv9002 spi1.0: Set intf delay clk:3, d:2, tx:0 c:0
    [   33.417034] adrv9002 spi1.0: Set intf delay clk:3, d:3, tx:0 c:0
    [   33.426543] adrv9002 spi1.0: Set intf delay clk:3, d:4, tx:0 c:0
    [   33.435789] adrv9002 spi1.0: Set intf delay clk:3, d:5, tx:0 c:0
    [   33.444999] adrv9002 spi1.0: Set intf delay clk:3, d:6, tx:0 c:0
    [   33.454591] adrv9002 spi1.0: Set intf delay clk:3, d:7, tx:0 c:0
    [   33.464675] adrv9002 spi1.0: Set intf delay clk:4, d:0, tx:0 c:0
    [   33.474218] adrv9002 spi1.0: Set intf delay clk:4, d:1, tx:0 c:0
    [   33.484084] adrv9002 spi1.0: Set intf delay clk:4, d:2, tx:0 c:0
    [   33.493427] adrv9002 spi1.0: Set intf delay clk:4, d:3, tx:0 c:0
    [   33.503045] adrv9002 spi1.0: Set intf delay clk:4, d:4, tx:0 c:0
    [   33.513130] adrv9002 spi1.0: Set intf delay clk:4, d:5, tx:0 c:0
    [   33.522781] adrv9002 spi1.0: Set intf delay clk:4, d:6, tx:0 c:0
    [   33.533038] adrv9002 spi1.0: Set intf delay clk:4, d:7, tx:0 c:0
    [   33.542488] adrv9002 spi1.0: Set intf delay clk:5, d:0, tx:0 c:0
    [   33.552568] adrv9002 spi1.0: Set intf delay clk:5, d:1, tx:0 c:0
    [   33.561937] adrv9002 spi1.0: Set intf delay clk:5, d:2, tx:0 c:0
    [   33.571893] adrv9002 spi1.0: Set intf delay clk:5, d:3, tx:0 c:0
    [   33.580854] adrv9002 spi1.0: Set intf delay clk:5, d:4, tx:0 c:0
    [   33.590347] adrv9002 spi1.0: Set intf delay clk:5, d:5, tx:0 c:0
    [   33.600308] adrv9002 spi1.0: Set intf delay clk:5, d:6, tx:0 c:0
    [   33.609577] adrv9002 spi1.0: Set intf delay clk:5, d:7, tx:0 c:0
    [   33.619272] adrv9002 spi1.0: Set intf delay clk:6, d:0, tx:0 c:0
    [   33.629729] adrv9002 spi1.0: Set intf delay clk:6, d:1, tx:0 c:0
    [   33.639594] adrv9002 spi1.0: Set intf delay clk:6, d:2, tx:0 c:0
    [   33.649110] adrv9002 spi1.0: Set intf delay clk:6, d:3, tx:0 c:0
    [   33.658757] adrv9002 spi1.0: Set intf delay clk:6, d:4, tx:0 c:0
    [   33.668942] adrv9002 spi1.0: Set intf delay clk:6, d:5, tx:0 c:0
    [   33.678591] adrv9002 spi1.0: Set intf delay clk:6, d:6, tx:0 c:0
    [   33.688737] adrv9002 spi1.0: Set intf delay clk:6, d:7, tx:0 c:0
    [   33.698314] adrv9002 spi1.0: Set intf delay clk:7, d:0, tx:0 c:0
    [   33.708382] adrv9002 spi1.0: Set intf delay clk:7, d:1, tx:0 c:0
    [   33.717871] adrv9002 spi1.0: Set intf delay clk:7, d:2, tx:0 c:0
    [   33.727752] adrv9002 spi1.0: Set intf delay clk:7, d:3, tx:0 c:0
    [   33.737056] adrv9002 spi1.0: Set intf delay clk:7, d:4, tx:0 c:0
    [   33.746785] adrv9002 spi1.0: Set intf delay clk:7, d:5, tx:0 c:0
    [   33.756842] adrv9002 spi1.0: Set intf delay clk:7, d:6, tx:0 c:0
    [   33.766441] adrv9002 spi1.0: Set intf delay clk:7, d:7, tx:0 c:0
    [   33.777912] adrv9002 spi1.0: cfg test stop:1, ssi:2, c:0, tx:0
    [   33.779763] adrv9002 spi1.0: RX: Got clk: 0, data: 4
    [   33.779917] adrv9002 spi1.0: Set intf delay clk:0, d:0, tx:1 c:0
    [   33.797493] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   33.810962] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   33.811496] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   33.811556] adrv9002 spi1.0: Set intf delay clk:0, d:1, tx:1 c:0
    [   33.826318] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   33.838976] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   33.839372] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   33.839419] adrv9002 spi1.0: Set intf delay clk:0, d:2, tx:1 c:0
    [   33.855760] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   33.870020] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   33.870563] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   33.870624] adrv9002 spi1.0: Set intf delay clk:0, d:3, tx:1 c:0
    [   33.888652] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   33.905047] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   33.905591] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   33.905651] adrv9002 spi1.0: Set intf delay clk:0, d:4, tx:1 c:0
    [   33.924199] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   33.940476] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   33.941006] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   33.941066] adrv9002 spi1.0: Set intf delay clk:0, d:5, tx:1 c:0
    [   33.958823] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   33.975877] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   33.976421] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   33.976481] adrv9002 spi1.0: Set intf delay clk:0, d:6, tx:1 c:0
    [   33.994546] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.011485] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.012191] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.012252] adrv9002 spi1.0: Set intf delay clk:0, d:7, tx:1 c:0
    [   34.030475] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.047298] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.047901] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.047962] adrv9002 spi1.0: Set intf delay clk:1, d:0, tx:1 c:0
    [   34.065133] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.081407] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.081944] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.082002] adrv9002 spi1.0: Set intf delay clk:1, d:1, tx:1 c:0
    [   34.100146] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.115396] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.116085] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.116146] adrv9002 spi1.0: Set intf delay clk:1, d:2, tx:1 c:0
    [   34.134245] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.151011] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.151547] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.151607] adrv9002 spi1.0: Set intf delay clk:1, d:3, tx:1 c:0
    [   34.169843] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.186277] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.186808] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.186867] adrv9002 spi1.0: Set intf delay clk:1, d:4, tx:1 c:0
    [   34.198369] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.207291] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.207592] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.207628] adrv9002 spi1.0: Set intf delay clk:1, d:5, tx:1 c:0
    [   34.216514] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.226328] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.226604] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.226641] adrv9002 spi1.0: Set intf delay clk:1, d:6, tx:1 c:0
    [   34.234524] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.243355] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.243703] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.243747] adrv9002 spi1.0: Set intf delay clk:1, d:7, tx:1 c:0
    [   34.252327] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.260586] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.260860] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.260885] adrv9002 spi1.0: Set intf delay clk:2, d:0, tx:1 c:0
    [   34.269174] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.280248] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.280491] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.280515] adrv9002 spi1.0: Set intf delay clk:2, d:1, tx:1 c:0
    [   34.287106] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.294408] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.294633] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.294658] adrv9002 spi1.0: Set intf delay clk:2, d:2, tx:1 c:0
    [   34.301924] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.310213] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.310443] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.310467] adrv9002 spi1.0: Set intf delay clk:2, d:3, tx:1 c:0
    [   34.317178] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.324344] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.324570] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.324593] adrv9002 spi1.0: Set intf delay clk:2, d:4, tx:1 c:0
    [   34.331199] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.338438] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.338660] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.338685] adrv9002 spi1.0: Set intf delay clk:2, d:5, tx:1 c:0
    [   34.345293] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.352445] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.352670] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.352694] adrv9002 spi1.0: Set intf delay clk:2, d:6, tx:1 c:0
    [   34.359920] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.367562] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.367787] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.367861] adrv9002 spi1.0: Set intf delay clk:2, d:7, tx:1 c:0
    [   34.375167] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.383362] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.383591] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.383615] adrv9002 spi1.0: Set intf delay clk:3, d:0, tx:1 c:0
    [   34.391554] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.399326] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.399555] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.399579] adrv9002 spi1.0: Set intf delay clk:3, d:1, tx:1 c:0
    [   34.407554] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.415628] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.415913] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.415937] adrv9002 spi1.0: Set intf delay clk:3, d:2, tx:1 c:0
    [   34.423112] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.430880] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.431110] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.431134] adrv9002 spi1.0: Set intf delay clk:3, d:3, tx:1 c:0
    [   34.438970] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.447037] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.447262] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.447286] adrv9002 spi1.0: Set intf delay clk:3, d:4, tx:1 c:0
    [   34.455188] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.463371] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.463599] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.463623] adrv9002 spi1.0: Set intf delay clk:3, d:5, tx:1 c:0
    [   34.471590] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.479335] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.479560] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.479583] adrv9002 spi1.0: Set intf delay clk:3, d:6, tx:1 c:0
    [   34.487439] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.495230] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.495457] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.495481] adrv9002 spi1.0: Set intf delay clk:3, d:7, tx:1 c:0
    [   34.502903] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.511072] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.511300] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.511324] adrv9002 spi1.0: Set intf delay clk:4, d:0, tx:1 c:0
    [   34.519294] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.527475] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.527702] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.527726] adrv9002 spi1.0: Set intf delay clk:4, d:1, tx:1 c:0
    [   34.534919] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.542646] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.542871] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.542895] adrv9002 spi1.0: Set intf delay clk:4, d:2, tx:1 c:0
    [   34.550538] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.558428] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.558655] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.558678] adrv9002 spi1.0: Set intf delay clk:4, d:3, tx:1 c:0
    [   34.566186] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.574033] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.574260] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.574284] adrv9002 spi1.0: Set intf delay clk:4, d:4, tx:1 c:0
    [   34.581486] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.589167] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.589393] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.589417] adrv9002 spi1.0: Set intf delay clk:4, d:5, tx:1 c:0
    [   34.596815] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.604483] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.604708] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.604731] adrv9002 spi1.0: Set intf delay clk:4, d:6, tx:1 c:0
    [   34.611957] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.619552] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.619778] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.619839] adrv9002 spi1.0: Set intf delay clk:4, d:7, tx:1 c:0
    [   34.626882] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.634842] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.635067] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.635091] adrv9002 spi1.0: Set intf delay clk:5, d:0, tx:1 c:0
    [   34.642087] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.649881] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.650107] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.650130] adrv9002 spi1.0: Set intf delay clk:5, d:1, tx:1 c:0
    [   34.657700] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.665477] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.665703] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.665727] adrv9002 spi1.0: Set intf delay clk:5, d:2, tx:1 c:0
    [   34.673078] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.680765] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.680991] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.681015] adrv9002 spi1.0: Set intf delay clk:5, d:3, tx:1 c:0
    [   34.687697] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.696011] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.696237] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.696261] adrv9002 spi1.0: Set intf delay clk:5, d:4, tx:1 c:0
    [   34.703467] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.711220] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.711444] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.711468] adrv9002 spi1.0: Set intf delay clk:5, d:5, tx:1 c:0
    [   34.719288] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.727270] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.727498] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.727521] adrv9002 spi1.0: Set intf delay clk:5, d:6, tx:1 c:0
    [   34.735334] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.743077] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.743302] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.743326] adrv9002 spi1.0: Set intf delay clk:5, d:7, tx:1 c:0
    [   34.751210] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.759382] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.759608] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.759632] adrv9002 spi1.0: Set intf delay clk:6, d:0, tx:1 c:0
    [   34.767580] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.775840] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.776067] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.776091] adrv9002 spi1.0: Set intf delay clk:6, d:1, tx:1 c:0
    [   34.782691] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.790420] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.790646] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.790670] adrv9002 spi1.0: Set intf delay clk:6, d:2, tx:1 c:0
    [   34.798341] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.806287] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.806515] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.806538] adrv9002 spi1.0: Set intf delay clk:6, d:3, tx:1 c:0
    [   34.813838] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.821797] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.822024] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.822048] adrv9002 spi1.0: Set intf delay clk:6, d:4, tx:1 c:0
    [   34.829652] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.837401] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.837626] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.837649] adrv9002 spi1.0: Set intf delay clk:6, d:5, tx:1 c:0
    [   34.845091] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.852710] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.852936] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.852959] adrv9002 spi1.0: Set intf delay clk:6, d:6, tx:1 c:0
    [   34.860307] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.868005] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.868230] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.868254] adrv9002 spi1.0: Set intf delay clk:6, d:7, tx:1 c:0
    [   34.875422] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.883052] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.883279] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.883303] adrv9002 spi1.0: Set intf delay clk:7, d:0, tx:1 c:0
    [   34.891169] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.898795] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.899021] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.899045] adrv9002 spi1.0: Set intf delay clk:7, d:1, tx:1 c:0
    [   34.906899] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.914414] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.914640] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.914664] adrv9002 spi1.0: Set intf delay clk:7, d:2, tx:1 c:0
    [   34.922427] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.930194] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.930423] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.930447] adrv9002 spi1.0: Set intf delay clk:7, d:3, tx:1 c:0
    [   34.938211] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.946194] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.946420] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.946444] adrv9002 spi1.0: Set intf delay clk:7, d:4, tx:1 c:0
    [   34.953368] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.961170] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.961396] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.961420] adrv9002 spi1.0: Set intf delay clk:7, d:5, tx:1 c:0
    [   34.968871] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.976658] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.976885] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.976909] adrv9002 spi1.0: Set intf delay clk:7, d:6, tx:1 c:0
    [   34.984231] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   34.991971] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.992196] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   34.992219] adrv9002 spi1.0: Set intf delay clk:7, d:7, tx:1 c:0
    [   34.999349] adrv9002 spi1.0: cfg test stop:0, ssi:2, c:0, tx:1
    [   35.007488] adrv9002 spi1.0: [c1]: d_e:0, f_f:0 f_e:1, s_e:0
    [   35.007713] adrv9002 spi1.0: [c2]: d_e:0, f_f:0 f_e:1, s_e:0
    [   35.008318] adrv9002 spi1.0: cfg test stop:1, ssi:2, c:0, tx:1
    [   35.009333] adrv9002 spi1.0: TX: Got clk: 0, data: 4
    [   35.022221] adrv9002 spi1.0: adrv9002-phy Rev 12.0, Firmware 0.22.49,  Stream 0.7.15.0,  API version: 68.16.2 successfully initialized
    [   35.026891] cf_axi_adc 84a00000.axi-adrv9002-rx-lpc: ADI AIM (10.03.\x00) probed ADC ADRV9002 as MASTER
    [   35.028806] cf_axi_tdd 84a0c800.axi-adrv9002-core-tdd-lpc: Analog Devices CF_AXI_TDD MASTER (1.00.a)
    [   35.045182] cf_axi_dds 84a02000.axi-adrv9002-tx-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.02.b) at 0x84A02000 mapped to 0x00000000a46f60d1, probed DDS ADRV9002

    I should have verified in the beginning, but as it turns out the carrier has VERY terrible skew and length mismatch between lanes of each channel (upwards of 150ps). The way I understand interface tuning to be implemented, the driver only attempts to correct skew between the clock and ALL the data lanes. So it cannot address skew say between strobe and I or Q.

    To fix I tied off the IO Delay Control registers, and instead hard coded delay values directly to compensate for the skew. This means when the driver goes to sweep the delay parameters its not actually changing anything in the PL, all combinations of values it uses should give the same result. Based on the logs this change (combined with flipping polarity in HDL) seems to have got interface tuning to pass. 

    That LED is still off however, not sure about that one. Will perform more testing and report back. 

  • Hello,
    Sorry for how long it took to get back to you.

    okay that's a very a high skew; how many lanes are you using, and what is your sample rate? It seems you've passed SSI tuning, are you able to actually transmit and receive data?

     

     

    On the LED, not seeing a green isn't the end of the world, however, it would be very bad if you were seeing a red LED, do you see a red LED? Can you probe the 1.8v pins on your carrier

  • Yeah was able to play and receive tones coherently after correcting the skew with HDL delays.