[Baremetal] How to configure ADRV9002 HDL IP for controlling two ADRV9002 ICs?

Question

In a previous post named "MCS--2 adrv9002s--one cpu", I was told that I only need one instance of the adrv9002 hdl ip to control/communicate with two adrv9002 ICs. When I looked at the Vivado adrv9002 hdl ip re-customization gui, it wasn't obvious how to configure the IP for controlling multiple adrv9002 ICs. 
 How would I set up the adrv9002 hdl ip to handle data and control for two adrv9002s? 
 
 I want the ability to receive from all Rx channels and transmit through all Tx channels in parallel. 
 No need to explain the SPI setup or DMA structure needed to acheive this.

RahulMushini · Accepted Answer

Hi, 
 
 We are currently working on the reference design, which is included in the SDK package. However, in the latest SDK release I noticed, the HDL files are missing. For your convenience, I&rsquo;m attaching the HDL files here. 
 You can find the HDL for communicating with two Navassa devices under the project name &ldquo;adrv9001x2_zcu102.&rdquo; Please note that this reference design has not been fully tested, so if it does not work as intended, you may need to implement your own work around. 
 
 Regards 
 Rahul 
 
 FPGA_Source_Code.zip)

RahulMushini · Answer

Hi, 
 A single instance of FPGA IP is required that can communicate with both Navassa devices. Currently, we don&rsquo;t have any example or reference design available, but we are working on it. At this time, there is no defined timeline for its release, so you will need to develop the IP to handle communication with both ADRV9002 devices. 
 
 Regards 
 Rahul

SLA Status	Assignee	Support Status
SLA Closed. Met after 15 hours	Ruairí SJagini	Awaiting Company Response

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[Baremetal] How to configure ADRV9002 HDL IP for controlling two ADRV9002 ICs?

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