[Baremetal] How to configure ADRV9002 HDL IP for controlling two ADRV9002 ICs?

Hi, 

A single instance of FPGA IP is required that can communicate with both Navassa devices. Currently, we don’t have any example or reference design available, but we are working on it. At this time, there is no defined timeline for its release, so you will need to develop the IP to handle communication with both ADRV9002 devices.

Regards

Rahul

Hi, 

A single instance of FPGA IP is required that can communicate with both Navassa devices. Currently, we don’t have any example or reference design available, but we are working on it. At this time, there is no defined timeline for its release, so you will need to develop the IP to handle communication with both ADRV9002 devices.

Regards

Rahul

Ok, just to clarify. Are you saying that the current adrv9002 HDL IP cannot handle communication with two adrv9002s? 

And therefore I must modify the currently available IP to support two adrv9002s?

Hi, 

We are currently working on the reference design, which is included in the SDK package. However, in the latest SDK release I noticed, the HDL files are missing. For your convenience, I’m attaching the HDL files here.

You can find the HDL for communicating with two Navassa devices under the project name “adrv9001x2_zcu102.” Please note that this reference design has not been fully tested, so if it does not work as intended, you may need to implement your own work around.

Regards

Rahul

FPGA_Source_Code.zip

Thanks:)

Has this project been renamed as "adrv9001_dual" in the ADI hdl repo?