MCS--2 adrv9002s--one cpu

Hi, 

Yes, synchronizing two ADRV9002 devices is achievable using the MCS (Multi-Chip Synchronization) feature. Your outlined steps are generally correct. However, please ensure that the MCS pulses reach both ADRV9002 devices within the same clock cycle to maintain proper synchronization. Additionally, it's important to verify that both the FPGA and the clock distribution chip are synchronized to avoid timing mismatches.

Regards

Rahul

What kind of timing mismatches will occur if the fpga-produced MCS signal and the dev_clk signal are not synchronized?

Is there a document that describes this "timing mismatch" hazard?

Please note one important aspect of the question above is "using a single zynq us+ mpsoc APU core". Are there any problems or caveats with connecting two ADRV900x transceivers to a single ultrascale+? Can two distinct copies of the IP and SDK firmware coexist in the one device without issues?

Thanks for focusing this conversation on the "using a single zynq us+ mpsoc APU core" part of my post.

I do want to use two distinct copies of the ADRV9002 HDL IP, but I only want to use one copy of the ADRV9002 SDK firmware.

Do the available MCS api functions have a chip-select or ID variable that allows a single cpu to talk to multiple adrv9002 chips?

Hi,

To communicate with two ADRV9002 devices using a single Zynq UltraScale+ MPSoC APU core, you only need one instance of the ADRV9002 HDL IP that supports both devices. The same SDK firmware will be loaded onto each ADRV9002 chip.

However, to enable the FPGA to interact with both devices individually, you must configure two distinct chip-select lines. These chip-selects allow the MCS API functions to target each ADRV9002 separately, even though the firmware and API interface are shared.

Regards

Rahul

How would I set up the adrv9002 hdl ip to handle data and control for two adrv9002s?

I just looked at the adrv9002 hdl ip re-customization gui and it's not obvious.

I would like both adrv9002s to be able to pipe data through the HDL driver simultaneously.