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Why fewer tracking Cals when CPU clock rate / 4 ?

Thread Summary

The user asked why fewer tracking calibrations are requested in configure.c when the CPU clock rate is set to 'divide 4' in TES. The final answer explains that insufficient processor clock speed degrades tracking calibration, preventing the ARM core from handling the computational load, which is why WBPOLY cals are omitted.
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Category: Software
Product Number: ADRV9004
Software Version: 28

When setting the CPU clock rate to 'divide 4' in TES, why are fewer tracking cals then requested in configure.c ?  In particular, the WBPOLY cals are omitted.  Is this because the CPU doesn't then have the capacity to perform the cals or is the requirement for those cals then negated ?