ADRV9002
Recommended for New Designs
The ADRV9002 is a highly integrated RF transceiver that has dual-channel transmitters, dual-channel receivers, integrated synthesizers, and digital signal...
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ADRV9002 on Analog.com
Hello,
As per the title, what exactly does apdUpperThreshPeakExceededCnt / apdLowerThreshPeakExceededCnt actually count?
Is it samples?
Is it local maxima?
Are the peaks counted on the instantaneous power of the received signal or on the on the received signal amplitude?
Thank you in advance.
K.
Hi,
I'll look into this question. The user guide section 'Analog Peak Detector (APD)' gives some details on the general function of the detector.
Regards,
Conrad
Thank you Conrad.
I have already read the APD section in the user guide, but it didn't seem very helpful with regard to my issue.
Thank you Conrad.
I have already read the APD section in the user guide, but it didn't seem very helpful with regard to my issue.
Hi,
I've checked on your question now. When the APD upper threshold is triggered, it raises an internal flag. This flag is then counted digitally using the AGC clock (which is at the same rate as the system clock). The apdUpperThreshPeakExceededCnt is then the number of AGC clock cycle where the APD upper threshold is triggered.
Regards,
Conrad
Hi,
Thanks for your reply. I have a few more questions, though.
1) So the counter essentially counts samples of the received signal sampled at the AGC clock (184.32 MHz), that exceed the threshold I have set?
2) When exactly does the counter reset, and more specifically, when does it reset with fast attack is enabled?
As an example, let's say I have apdUpperThreshPeakExceededCnt=10
, and the AGC counts 4 clock cycles where the threshold is triggered, after which my signal level drops below the threshold again. Do these 10 samples need to be consecutive above the threshold? If, as in my example, the counter isn't completed and the level drops, does the counter reset? If not, when does it reset? Additionally, when fast attack is enabled, when does the counter reset?
Thanks,
K.
Any news regarding my last questions?
You got something for me?
Hi,
We are writing up an explanation for the question, we will get back to you.
Regards
Rahul
Automatic Gain Control (AGC) has two modes of operation
Note: Assume the clock counter limit is 8 clock cycle.
Normal Mode:
Figure 1: Normal Mode
Figure 1 illustrates the operation of the Normal mode AGC. During the first period, when the signal's peak power exceeds the threshold, the AGC clock counter begins counting. At some point within the first period (indicated in green), the AGC clock counter exceeds the required number of clock cycles. At the end of the first period, the attenuation levels are applied, reducing the signal's power below the threshold, and simultaneously, the AGC clock counter resets.
In the second period, the signal again crosses the threshold, causing the AGC counter to start counting the clock cycles. However, before the counter exceeds the required number of cycles, the signal’s power drops below the threshold. Since the AGC counter doesn’t reach the necessary count, the attenuation is not triggered, and by the end of the second period, the AGC counter resets.
Note: The 1st and 2nd periods are the gain update period which is set by the user in TES.
Fast Attack Mode:
Figure 2: Fast Attack Mode
In this case, the key difference is when the attenuation is applied. During the first period, the signal exceeds the threshold, causing the AGC clock counter to surpass the clock cycle limit, triggering the attenuation immediately and resets the AGC counter. At the end of the first period, again AGC counter resets.
In the second period, the signal once again exceeds the threshold, and the AGC clock counter reaches 4 clock cycles before the signal falls back below the threshold. After some time within the same period, the signal power rises above the threshold again, and the AGC clock counter continues counting, now reaching 10 clock cycles. This exceeds the AGC clock counter limit, triggering the attenuation. Here the AGC clock counter resets once the attenuation is triggered to take care of the situation where signal peak power goes above the threshold again within the same period as shown in the figure 2.
Regards
Rahul
Hi and thanks for the thorough reply. Through TES I have noticed that the lowest value I can set Gain Refresh Period to is 50.5us whether I have Fast Attack option enabled or not. Is that valid, is it really 50.5us the lowest value I can set it to when I have fast attack enabled or can it go even lower? Thank you.
Hi,
In fast attack mode, the update happens whenever the signal exceeds the threshold, causing the AGC clock counter to surpass the clock cycle limit.
Regards
Rahul
Hi,
You didn’t answer my question though. I was asking about the Gain Refresh Period which you have denoted with vertical dashed lines in Figure 2. Does it go lower than 50.5us when fast attack is enabled or not?
any news on my last question?